Silicon Laboratories Inc.

Motorola Corporation

Crystal Semiconductor Corporation

Maxim Integrated Products, Inc.

Charles D Thompson

Eric J Swanson

Joseph P Gergen

Mitchell Reid

Adrian Maxim

Salvador R Bernadas

Timothy Joseph Dupuis

Bradley Martin

Nicholas R Van Bavel

Michael Vayden Jenkins

Sangil Park

Garth D Hillman

Andrew W Dornbusch

Dion D Messer

Mark Albert Pinchback

Edward Kim Fung Lee

An integrated circuit () includes a semiconductor substrate () and an integrated circuit package (). The semiconductor substrate () has a first pair of bonding pads () conducting a differential output signal thereon and adapted to be coupled to an input of a first external filter, and a second pair of bonding pads () conducting a differential input signal thereon and adapted to be coupled to an output of said first external filter. The integrated circuit package () encapsulates the semiconductor substrate () and has first () and second () terminal pairs corresponding and coupled to the first () and second () pairs of bonding pads, respectively. The first () and second () terminal pairs are separated by a first predetermined distance is sufficient to maintain an input-to-output isolation therebetween of at least a first predetermined amount.

Integrated circuit suitable for use in radio receivers

A receiver () includes a mixing digital-to-analog converter (DAC) (), a direct digital frequency synthesizer (DDFS) (A) and an interface (D). The mixing DAC () includes a radio frequency (RF) transconductance section () and a switching section (). The RE transconductance section () includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section () is coupled to the RF transconductance section () and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (). The interface (D) is coupled to the DDFS (A) and is configured to align the bits provided by the DDFS (A) with a first clock signal.

Interface/synchronization circuits for radio frequency receivers with mixing DAC architectures

A receiver () includes a first mixing digital-to-analog converter (DAC) (), a second mixing DAC (), a direct digital frequency synthesizer (DDFS) (), a phase correction circuit (), a selectable load () and a magnitude correction circuit (). The first mixing DAC () includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC () includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS () is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit () is configured to provide a phase correction signal to a control input of the DDFS (). The first selectable load () includes an input coupled to the output of the first mixing DAC () and a control input. The magnitude correction circuit () is configured to provide a first magnitude correction signal to the control input of the first selectable load ().

Techniques for performing gain and phase correction in a complex radio frequency receiver

A receiver () includes a transconductance mixer (), a polyphase filter (), and a transimpedance amplifier (). The transconductance mixer () mixes a radio frequency (RF) voltage signal into a current signal having a plurality of phases using a local oscillator signal. The polyphase filter () filters the current signal to provide a filtered current signal. The transimpedance amplifier () converts the filtered current signal into an output voltage signal.

Low noise image reject mixer and method therefor

A receiver includes a tuner and a circuit. The tuner receives an indication of a radio frequency signal from an antenna feedline in response to the radio frequency signal being provided to the antenna feedline by an amplifier. The circuit transmits a control signal to the antenna feedline to control a gain of the amplifier in response to a strength of the radio frequency signal.

Controlling the gain of a remote active antenna

A surge clamp circuit that may be implemented with DAA circuitry to limit the total voltage developed across one or more line side capacitors due to charge pumping phenomenon during a multi-transient events such as lightning strikes. The surge clamp circuit is capable of electronically sensing a transient event (e.g., lightning strike) and of momentarily turning on one or more components of a DAA hookswitch circuit during on hook mode to discharge the voltage developed across one or more line side capacitors before it reaches critical breakdown levels. The surge clamp circuit may be configured with a clamping sensitivity selected so that the DAA hookswitch circuitry is only activated or turned on upon occurrence of relatively large and potentially damaging transient events, and not upon occurrence of non-damaging transient events, such as operational signals.

Surge clamp protection circuit

A system includes a first antenna that is located on one side of a motor vehicle and a second antenna that is located on another side of the motor vehicle. The system includes a controller, a switch and a receiver. In response to a heading of the motor vehicle, the controller selectively couples the receiver to one of the first antenna and the second antenna.

Mobile satellite receiver system

The present invention comprises a method and apparatus for boosting an input signal to an output signal with a variable gain according to a supply voltage. The circuit comprises a detector and a voltage booster. The detector detects the supply voltage and generates a control signal having a value dependent on a difference between the detected supply voltage and a critical supply voltage. The critical supply voltage is temperature insensitive. The voltage booster is coupled to the detector for generating an output signal having a gain relative to the input signal. The gain is dependent on the value of the control signal.

Boosting circuit with supply-dependent gain

The present invention relates to a tone signal generator. The tone signal generator includes first tone signal generation means for producing a dual-tone, multi-frequency ('DTMF') audio signal; second tone signal means for producing a plurality of non-DTMF audio signals; storage means for storing data that represents at least one channel of an output audio tone signal; and selection means for selectively loading the DTMF signal into the storage means and for selectively accumulating the non-DTMF signals into the storage means so as to generate the output tone signal.

Tone signal generator for producing multioperator tone signals

The output gates of a delta-sigma modulator can generate i(t) transient signal in the power supply lines of a delta-sigma modulator. These i(t) spikes, which would otherwise produce non-linearities which can be coupled into the frequency band of interest of the modulator, are made to be linear by using return-to-zero data encoding and by providing multi-bit outputs to the delta-sigma modulator in which the output states all have equal numbers of logic ones at the output lines for each of the output states.

Low noise transmission of output data from a delta-sigma modulator

The thermal noise generated through the feedback capacitor of a delta-sigma modulator is attenuated by transferring a reference voltage through the capacitor in two separate steps during each sampling period. This permits a reduction in the size of the feedback capacitor, thereby reducing thermal noise, without increasing the voltage on the switching capacitors on the summing node side of the feedback capacitors which would induce degradation due to hot electron effects.

Detent switching of summing node capacitors of a delta-sigma modulator

An analog-to-digital converter includes a two-bit delta-sigma modulator. The delta-sigma modulator is comprised of a first stage integrator (10) that feeds a noise shaping circuit (18). The output of the noise shaping circuit (18) is input to a two-threshold imbedded ADC (20) to provide the two-bit output. This output of the imbedded ADC (20) is input to a digital filter (22) to provide the filtered digital output, this filtering high-frequency noise. The output of the imbedded ADC (20) is also fed back through a three-level DAC (24) to a summing junction on the input of the integrator (10). The three-level DAC 24 has three states that are output with one state being a 'do nothing' state. The thermal noise performance of the delta-sigma modulator as a function of the quantizer threshold voltages is first simulated and then the value of the quantizer thresholds selected to provide optimum signal-to-thermal noise performance.

Delta-sigma modulator for an analog-to-digital converter with low

A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta. coefficient is stored in a block (16) and is generated during a calibration cycle by a .delta. processor (39). The .delta. processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the .delta. coefficient is frozen and the calibration multiplexer (10) selects the analog input.

Method and apparatus for calibrating a multi-bit delta-sigma modular

A analog to digital (A/D) conversion system (10 or 20) receives a modulated analog signal, translates the frequency of the signal to a lower frequency, and converts the analog signal to a filtered digital signal. In one form, the conversion system (10) has an analog signal multiplier (16), and A/D converter (18), an oscillator (12) and a frequency divider (14). Frequency multiplier (16) translates the frequency of the analog signal, and A/D converter (18) converts the analog signal to digital form. Frequency divider (14) receives a clock signal from oscillator (12) and divides the frequency of the clock signal. Because the same clock signal is used for frequency translation and analog to digital conversion, a phase error is not introduced in the output digital signal. Additionally, the frequency divider (14) forces the frequencies of the analog and digital signals to be an integer ratio for subsequent demodulation.

Frequency translating coherent analog to digital conversion system for

An oversampling analog-to-digital converter is responsive to an analog input signal for providing a digital output signal representative of the magnitude of the analog input signal at an output bus. The analog input signal is quantized through a sigma delta modulator stages for providing first and second digital output signals which are recombined through at least first and second digital integrators and at least first and second digital differentiators of a low pass comb filter for providing the digital output signal. The first digital output signal controls the application of either a digital correction signal or digital zeroes to the least significant portion of a predetermined number of accumulator cells of the first digital integrator thereby substituting the digital correction signal for the digital output signal to weight the latter's contribution and compensate for the quantization error which increases the resolution of the digital output signal.

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Buda, TX, United States of America

Charles D Thompson