Hewlett-packard Development Company, L.p.

Charles Corey Pie

Gregory L Ranson

Samuel D Naffziger

Timothy Charles Fischer

Eric Matthew Lee

A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.

Integrated circuit analysis method and program product

Systems, software products and methods generate test vectors to analyze cells of electronic gates. A cell of a cell library is electronically selected. Input combinations of stimuli for the cell are determined. One or more input combinations are removed that do not affect maximum and minimum signal propagation timing through the cell. Test vectors for the cell are generated based upon remaining input combinations.

Systems and methods for generating test vectors to analyze cells of electronic gates

The present invention is directed to a method for evaluating a circuit design to identify potential race conditions including the steps of identifying switching elements in a design, storing control node and switched node pair information for each of the switching elements, identifying stacks of the switching elements; storing information about the stacks of switching elements; identifying parallel connected ones of the switching elements; identifying parallel stacks; and calculating a combined switching current for the parallel switching elements and stacks.

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Fort Collins, CO, United States of America

Charles Corey Pie