Altera Corporation

Plethron Inc.

Charles Chu

Jeffrey T Watt

Bradley Jensen

Antonio Gallerano

Eric Minami

Jeffrey Xiaoqi Tung

The present disclosure generally relates to laser range finders. In one embodiment, a shallow-trench isolation diode operates in a reverse-biased mode. In another embodiment, a poly-defined diode operates in a forward-biased mode. In both embodiments, the diode emits photons in response to a radio frequency current, and the photons are received by an avalanche photo diode during a calibration process.

Injecting an RF local oscillator signal into an avalanche photo diode using photons emitted from a light emitting diode

The invention relates to capturing a still or moving image as well as object position and displacement data for the image, storing the image and the data as a dimension extractable object, and utilizing the dimension extractable object. In one embodiment, the dimension extractable object is used in a method of stitching a plurality of images together to form a stitched image. In another embodiment, the dimension extractable object is used in a method of generating a stitched image from a video image. In another embodiment, the dimension extractable object is used in a method of generating a three-dimensional model from a video image.

Generating a stitched image or three-dimensional model from one or more dimension extractable objects comprising spatial metadata for a captured image or video

Embodiments of the present disclosure use an 'on chip' silicon LED to generate a light signal for calibration of a range finder. The light signal from the silicon LED may be detected by photo detectors in a reference path and a receive path of the range finder to generate a calibration phase offset, which may be subtracted out from a phase offset measurement of the range finder to correct the phase offset measurement for component mismatch due to, for example, environment, process variation, aging, etc.

Using integrated silicon LED to calibrate phase offset in optical receiver in laser range finder

The invention relates to capturing a still or moving image as well as object position and displacement data for the image, storing the image and the data as a dimension extractable object, and utilizing the dimension extractable object.

Dimension extractable object comprising spatial metadata for a captured image or video

In one embodiment, an integrated circuit includes an input-output circuit, first and second electrostatic discharge diode circuits, first and second power clamp circuits and first, second and third voltage rails. The input-output circuit includes an input node that is coupled to an input-output pad. The first electrostatic discharge diode circuit may be coupled between the first and third voltage rails whereas the second electrostatic discharge diode circuit may be coupled between the second and third voltage rails. In addition to that, the first voltage rail may also be coupled to the first power clamp circuit and the second voltage rail may also be coupled to the second power clamp circuit.

Electrostatic discharge circuitry with separate power rails

A multi-fingered gate transistor formed in a substrate of one conductivity type overlying a well of a second conductivity type. Ohmic contact to the well is made by an implanted region of the second conductivity type that circumscribes the gate transistor. Ohmic contact to the substrate is made by taps located on sides of the gate structure between the gate structure and the well contact. Floating wells are located on opposite sides of the gate structure between the substrate taps and the ends of the gates to isolate these substrate taps and force current flow in the substrate under the gate transistor to be substantially perpendicular to the direction in which the gate fingers extend. This increases the potential difference between these substrate regions and source regions in the gate transistor, thereby aiding the triggering of the parasitic bipolar transistors under adjacent gate fingers into a high current state.

ESD protection circuit

Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. The ESD protection circuitry does not include polysilicon resistors. The ESD protection circuitry may include n-channel transistors coupled in parallel between an output node that is connected to an input/output pin and a ground terminal. The n-channel transistors may each have a drain terminal that is coupled to the output node through first metal paths and a source terminal that is coupled to the ground terminal through second metal paths. The first and second metal paths may be routed over gate terminals of the respective n-channel transistors to provide sufficient resistance. The first and second metal paths may provide desired pull-down resistance in the ESD protection circuitry so that the ESD protection circuitry can sink sufficient current through each of the n-channel transistors to protect internal circuitry from damage in an ESD event.

Electrostatic discharge protection circuitry

In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.

ESD protection for differential output pairs

Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.

Integrated circuit guard rings

Circuits and techniques for operating a memory cell on an integrated circuit (IC) are disclosed. A disclosed memory cell includes a first inverter coupled to a second inverter to form a first connection and a second connection. The first connection is operable to receive at least a first data signal at a first voltage and the second connection is operable to receive at least a second data signal at a second voltage. A first oxide capacitor and a second oxide capacitor are coupled to the first and second connections respectively. Both the first and second oxide capacitors are coupled to receive a programming signal at a third voltage that may be operable to rupture either one of the first or second oxide capacitor.

Circuits and methods for hardening volatile memory circuits through one time programming

A multi-fingered gate transistor is disclosed that is formed in a substrate of one conductivity type overlying a well of a second conductivity type. Ohmic contact to the well is made by an implanted region of the second conductivity type that circumscribes the multi-fingered gate transistor. Ohmic contact to the substrate is made by four taps located on four sides of the multi-fingered gate structure between the gate structure and the well contact. Floating wells are located on opposite sides of the gate structure between two of the substrate taps and the ends of the gates to isolate these substrate taps and force current flow in the substrate under the multifingered gate transistor to be substantially perpendicular to the direction in which the gate fingers extend. This increases the potential difference between these substrate regions and adjacent source regions in the multi-fingered gate transistor, thereby aiding the triggering of the parasitic bipolar transistors under adjacent gate fingers into a high current state. This also reduces the differences among the potentials in the substrate under the different source regions and thus improves the uniformity of turn-on of the parasitic bipolar transistors. As a result, it is not necessary to maintain as great a distance from the isolated substrate taps as in prior art devices. Moreover, because the floating wells significantly improve the performance of the ESD protection structure, some of this performance improvement may be exchanged for decreases in the size of the protection structure.

Growing community of inventors

Cupertino, CA, United States of America

Charles Chu