Taiwan Semiconductor Manufacturing Comp. Ltd.

Nvidia Corporation

Comp-Any Gmbh

Charles Chew-Yuen Young

Chih-Liang Chen

Jiann-Tyng Tzeng

Kam-Tou Sio

Chih-Ming Lai

Ru-Gun Liu

Wei-Cheng Lin

Shih-Wei Peng

Hui-Ting Yang

Chun-Kuang Chen

Jack Liu

Lei-Chun Chou

Ge Yang

Hwong-Kwo Lin

Shun Li Chen

Meng-Hung Shen

Cheng-Chi Chuang

Yung-Sung Yen

Wei-Liang Lin

Chin-Yuan Tseng

Chia-Tien Wu

Hui-Zhong Zhuang

Wen-Hao Chen

Chi-Yeh Yu

Shun-Li Chen

Shu-Hui Sung

L C Chou

Tien-Lu Lin

Wei-Hao Wu

Yi-Hsun Chiu

Kam-tou Sio

Sing-Kai Huang

Ethan A Frazier

Ching-Wei Tsai

Chia-Hao Chang

Shi Ning Ju

Pin-Dai Sue

Yi-Hsiung Lin

Hsin-Chih Chen

Ko-Bin Kao

Ho Che Yu

Wei-Chen Chien

Hwong-Kwo (Hank) Lin

Praneeth Narayanasetti

Kuo-Cheng Chiang

Wei-Cheng Wu

Tsong-Hua Ou

Wei-An Lai

Chun-Hung Liou

Meng-hung Shen

Guoqing Ning

Wayne Lai

Kuo-Cheng Ching

Chung-Hsing Wang

John Stephen Montrym

Yuan-Te Hou

Yi-Ming Sheu

James M Van Dyke

Chun-Fu Cheng

Yi-Chuin Tsai

Anthony Michael Tamasi

Shang-Wei Fang

Yi-Feng Chen

Yi-Han Wang

Helen Shu-Hui Chang

Beibei Ren

Bruce Cory

Stefan Scotzniovsky

Sean J Treicher

Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.

Asynchronous read circuit using delay sensing in magnetoresistive random access memory (MRAM)

A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Metal patterning for internal cell routing

A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Semiconductor device including source/drain contact having height below gate stack

In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.

Method and related apparatus for improving memory cell performance in semiconductor-on-insulator technology

A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.

Middle-end-of-line strap for standard cell

In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.

Silicon on insulator semiconductor device with mixed doped regions

The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Metal rail conductors for non-planar semiconductor devices

A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Buried metal for FinFET device and method

The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Method for routing local interconnect structure at same level as reference metal line

A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.

An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

Integrated circuit and method of manufacturing same

Asynchronous read circuit using delay sensing in magnetoresistive random access memory (mRAM)

A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

Method and system of manufacturing conductors and semiconductor device which includes conductors

Growing community of inventors

Cupertino, CA, United States of America

Charles Chew-Yuen Young