Lsi Logic Corporation

S3 Incorporated, Inc.

Vertex Semiconductor Corporation

Charles C Stearns

Stephanie W Ti

Karthikeyan Kannappan

Andrea Nguyen

Himanshu Jain

Olive T Tao

Charlene S Ku

Allen Lyu

Joe Yeun

Peng-Huat Ang

Soma Bhattacharjee

MPEG compressed video data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor (video decoder engine) in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator. The video decoder engine is a fast hardwired processor. It has a graceful degradation capability to allow dropping of occasional video frames without displaying any part of a dropped video frame. The video decoder engine has a three stage pipeline structure to minimize circuitry and speed up operation.

Video decoder engine

MPEG compressed data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator.

Decompression of MPEG compressed data in a computer system

Method and apparatus for decompression of MPEG compressed data in a

The frame reconstruction (FR) portion of an MPEG decompression circuit includes a horizontal interpolation element, a vertical interpolation element, and a selector (post processing) element. The horizontal and vertical interpolation elements are each digital filters averaging respectively two horizontal and two vertical adjacent pixels in an MPEG pixel block. Logic is included for constructing B, I, and P-type MPEG pictures. Also included is an error/warning handling mechanism.

Frame reconstruction for video data compression

Decompression of MPEG compressed audio data is performed in a computer system by the host processor in the computer system providing preprocessing data decompression and a dedicated audio decoder engine (which is a digital signal processor) performing the filtering and windowing of the host preprocessed data. The audio decoder engine includes a data path, instruction set, registers and internal program and data memory. The host performs a large portion of the audio decompression, leaving the windowing and filtering to the audio decoder engine. Thus the computationally intensive portions of the decompression are performed more efficiently. Coefficient storage in the audio decompression engine is optimized by taking advantage of the symmetries inherent in the coefficient data, both for the filter coefficients and the windowing coefficients. Double buffer input and output buffers speed the data flow between the host processor and the audio decoder engine. The double buffers allow a continuous flow of data from the host processor to the audio decoder engine.

Partitioned decompression of audio data using audio decoder engine for

Affine image transformations are performed in an interleaved manner, whereby coordinate transformations and intensity calculations are alternately performed incrementally on small portions of an image. The pixels are processed in rows such that after coordinates of a first pixel are determined for reference, each pixel in a row, and then pixels in vertically adjacent rows, are processed relative to the coordinates of the previously processed adjacent pixels. After coordinate transformation to produce affine translation, rotation, skew and/or scaling, intermediate metapixels are vertically split and shifted to eliminate holes and overlaps. Intensity values of output metapixels are calculated as being proportional to the sum of scaled portions of the intermediate metapixels which cover the output pixels respectively.

Apparatus for 2-D affine transformation of images

A novel technique for improving the accuracy of seed values for iterative convergent computations such as square-root taking and division by providing optional dynamic range expansion as a part of the seed selection process is described. The technique, by improving seed accuracy, reduces the number of iterations required for convergence. This is accomplished with less hardware than would be required to accomplish the same result with a large ROM.

Seed generation technique for iterative, convergent digital computations

Affine image transformations are performed in an interleaved manner, whereby coordinate transformations and intensity calculations are alternately performed incrementally on small portions of an image. The pixels are processed in rows such that after coordinates of a first pixel are determined for reference, each pixel in a row, and then pixels in vertically adjacent rows, are processed relative to the coordinates of the previously processed adjacent pixels. After coordinate transformation to produce affine translation, rotation, skew, and/or scaling, intermediate metapixels are vertically split and shifted to eliminate holes and overlaps. Intensity values of output metapixels are calculated as being proportional to the sum of scaled portions of the intermediate metapixels which cover the output pixels respectively.

Method for 2-D affine transformation of images

A write buffer having selective flush is disclosed. The write buffer has address buffers and associated data buffers and comparators. During a 'sneak read' operation, the address of the read operation is compared to the address signals stored in each of the address buffers. If a match is found, the read operation is temporarily suspended for only as long as the matched address remains stored in the write buffer. In a further improvement, the overhead associated with each match can be minimized to one write operation for each match before the matched address and data signals are written out of the write buffer.

Memory buffer having selective flush capability

A digital multiplier is configured from a number of identical circuit 'slices' with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of the space saving characteristics of array multipliers, with many of the speed advantages of tree multipliers. Various parameters of the design are flexible and may be changed by the designer to make speed versus size tradeoffs. The multiplier may be either pipelined or non-pipelined.

Digital multiplier based upon a regularly structured sum of products

A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline bubbles). This is accomplished with minimal additional circuitry over that required for conventional floating-point multipliers, and does not adversely affect the speed of iterative calculations. Method and apparatus are disclosed.

Interleaving operations in a floating-point numeric processor

Disclosed is a digital multiplier-accumulator circuit utilizing a carry save adder tree, pipeline register and carry select adder. Also disclosed is a digital multiplier circuit including a carry save adder tree and a pipeline register.

Digital multiplier circuit and a digital multiplier-accumulator circuit

A method to adjust the divisor and dividend, for application to a divider, so that the mantissa part of the divisor is transformed to be within a known limited range. The limiting of the transformed divisor range enables the complexity of the quotient select logic to be reduced accordingly. Once the divisor is restricted to the selected range, the dividend is adjusted proportionally so the quotient is unchanged.

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San Jose, CA, United States of America

Charles C Stearns