Intel Corporation

Charles C Phares

Yunhui Chu

John M Lynch

James A McCall

George Vergis

Xiang Li

John Lang

Jun Liao

Kevin Ceurter

Konika Ganguly

Fan Chen

Qin Li

A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

Memory channel having more than one DIMM per motherboard DIMM connector

Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is 'stuffed' (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty 'unstuffed' connectors from increasing error risks on active channels.

Connectors with switchable terminal loads

Aspects of the embodiments are directed to a data transmission receiver that includes a neural network circuit for resolving a received bit value. The data transmission receiver can be coupled to a data transmitter by a high speed data link. The neural network circuit can sample a bit value at multiple locations across the bit's unit interval. The neural network circuit can also sample bit values for neighboring bits to the interested bit at multiple sampling locations across unit intervals for the neighboring bits. The neural network circuit can determine the value of the interested bit from the samples of the waveform.

Neural network-based systems for high speed data links

Techniques and mechanisms to provide a connector for securing to a first printed circuit board (PCB). In an embodiment, the connector is configured to receive a second PCB, where a first hardware interface of the connector includes conductors to facilitate bilateral decoupling from (and coupling to) respective hardware interfaces of the first PCB and the second PCB. A first conductor of the first hardware interface includes a first portion configured to move, relative to a housing structure of the connector, in response to the connector receiving a portion of a device which comprises the second PCB. A second portion of the first conductor is configured to be brought into contact with a conductive pad of the device. In another embodiment, the connector includes housing structures configured to move relative to one another while the connector is secured to the first PCB.

Connector with structures for bi-lateral decoupling of a hardware interface

Growing community of inventors

Federal Way, WA, United States of America

Charles C Phares