Intel Corporation

Other

Micron Technology Incorporated

Stmicroelectronics S.r.l.

Ovonyx Inc.

University of California

Ovonyx Memory Technology, LLC

Charles C Kuo

Brian S Doyle

Kaan Oguz

Mark L Doczy

Robert S Chau

David L Kencke

Elijah V Karpov

Uday Shah

Kevin O'Brien

Satyarth Suri

Ilya V Karpov

Roksana Golizadeh Mojarad

Yudong Kim

Ravi Pillarisetty

Tyler A Lowrey

Prashant Majhi

Greg Atwood

Van H Le

Abhishek A Sharma

Roza Kotlyar

Niloy Mukherjee

Noriyuki Sato

Maria Santina Marangon

Jack T Kavalieros

Gilbert W Dewey

Willy Rachmady

Marko Radosavljevic

Justin Brockman

Arijit Raychowdhury

Arnab Sen Gupta

Juan G Alzate Vinasco

Clair C Webb

Tahir Ghani

Stanford R Ovshinsky

Matthew V Metz

Fabio Pellizzer

Han Wui Then

Seung Hoon Sung

Dmitri E Nikonov

Derchang Kau

Guy Charles Wicker

Yih Wang

Ward D Parkinson

Christopher J Wiegand

Sergey A Kostylev

Sey-Shing Sun

Eric R Dickey

Tejaswi K Indukuri

Urusa Alaan

Md Tofizur Rahman

George A Gordon

John M Peters

Michael Stephen Bowen

Sasikanth Manipatruni

Benjamin Chu-Kung

Tanay Gosavi

James W Tschanz

Stephen H Tang

Oleg Golonzka

Sean T Ma

Nicole K Thomas

Shriram Shivaraman

Scott Bruce Clendenning

Fatih Hamzaoglu

Gianpaolo Spadini

Nazila Haratipour

Justin R Weber

Angeline Smith

Ayan Kar

Daniel Ouellette

Benjamin Buford

I-Cheng Tung

Nicholas A Thomson

Sudarat Lee

Tsu-Jae Liu

Brian Maertz

Tobias Brown-Heft

Yong Ju Lee

Eric Charles Mattson

Thoe Michaelos

Benjamin Orr

Daniel Ouelette

Charles Mokhtarzadeh

Kevin P OBrien

Roksana Golizadeh Mojard

Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

ESD protection decoupled from diffusion

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vwithin the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

Monolithic memory stack

An integrated circuit includes one or more layers of insulating material defining a vertical bore with a first portion and a second portion. A capacitor structure is in the first portion of the vertical bore and includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. A transistor structure is in the second portion of the vertical bore and includes a third electrode extending into the second portion of the vertical bore, a layer of semiconductor material in contact with the first electrode and in contact with the second electrode, and a dielectric between the semiconductor material and the insulating material. A fourth electrode wraps around the transistor structure such that the dielectric is between the semiconductor material and the fourth electrode. The capacitor structure can be above or below the transistor structure in a self-aligned vertical arrangement.

Vertical memory cell with self-aligned thin film transistor

A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

3D memory array with memory cells having a 3D selector and a storage component

Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

Epitaxial layers on contact electrodes for thin- film transistors

Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

Digital-to-analog converters having multiple-gate transistor-like structure

A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.

Perpendicular spin transfer torque memory (pSTTM) devices with enhanced thermal stability and methods to form the same

An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.

Perpendicular spin transfer torque magnetic mechanism

A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.

Magnetic tunnel junction (MTJ) devices with a synthetic antiferromagnet (SAF) structure including a magnetic skyrmion

A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster has a magnetic material layer. The booster may further have an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to storebits/cell.

Multi-level magnetic tunnel junction (MTJ) devices including mobile magnetic skyrmions or ferromagnetic domains

A spin orbit torque (SOT) memory device includes an SOT electrode on an upper end of an MTJ device. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet and is coupled with a conductive interconnect at a lower end of the MTJ device. The SOT electrode has a footprint that is substantially the same as a footprint of the MTJ device. The SOT device includes a first contact and a second contact on an upper surface of the SOT electrode. The first contact and the second contact are laterally spaced apart by a distance that is no greater than a length of the MTJ device.

Spin orbit torque (SOT) memory device with self-aligned contacts and their methods of fabrication

A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack that includes a plurality of magnetic layers interleaved with a plurality of non-magnetic insert layers. The layers are arranged such that the topmost and bottommost layers are magnetic layers. The stacked design decreases the damping of the MTJ free magnetic stack, beneficially reducing the write current required to write to the pSTTM device. The stacked design further increases the interface anisotropy, thereby beneficially improving the stability of the pSTTM device. The non-magnetic interface layer may include tantalum, molybdenum, tungsten, hafnium, or iridium, or a binary alloy containing at least two of tantalum, molybdenum, tungsten hafnium, or iridium.

Perpendicular STTM multi-layer insert free layer

An integrated circuit comprising a self-aligned embedded phase change memory cell is described. In an example, the integrated circuit includes a bottom electrode. A conductive line is above the bottom electrode along a first direction above a substrate. A memory element is coupled between the bottom electrode and the conductive line, the memory element comprising a phase change material layer that is self-aligned with the conductive line.

Self-aligned embedded phase change memory cell having a fin shaped bottom electrode

A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material, where the SOT material includes iridium and manganese and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, a fixed layer and a tunnel barrier between the free layer and the fixed layer and a SAF structure above the fixed layer. The Ir&#x2014;Mn SOT material and the free magnet have an in-plane magnetic exchange bias.

Spin orbit torque (SOT) memory devices with enhanced tunnel magnetoresistance ratio and their methods of fabrication

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Union City, CA, United States of America

Charles C Kuo