International Business Machines Corporation

Charles C Hanson

Curtis Walter Preuss

Delbert Raymond Cecchi

Francis K King

Michael Joseph Ross

Gary Lee Dix

Robin Charles Jahnke

Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.

CMOS receiver for simultaneous bi-directional links

Methods and apparatus are provided for implementing a CMOS low voltage current source. The current source embodies a voltage feedback mechanism with a low voltage gain. The current source controls a gate of an output driver FET such that a substantially constant current is maintained, even for a portion of the linear range of operation of the output FET. The current source is suitable for driving transmission lines on printed wiring boards, or other application where the load is relatively heavy or complex, and where operation near the power supply is required.

Impedance enhancement circuit for CMOS low-voltage current source

A differential receiver-amplifier having reduced input distortion at differential input (positive and negative) terminals to the differential receiver-amplifier. The output from the differential receiver-amplifier is generated from a differential signal detector receiving each differential input from one of a pair of differential amplifiers. While each of the differential amplifiers have two differential input terminals of substantially different input impedances, the first differential input terminal of the first differential amplifier and the second differential input terminal of the second differential amplifier are coupled to the differential positive terminal, and the second differential input terminal of the first differential amplifier and the first differential input terminal of the second differential amplifier are coupled to the differential negative terminal, wherein the resulting input impedance at the differential positive terminal is substantially equal to the resulting input impedance at the differential negative terminal.

CMOS dual-stage differential receiver-amplifer

A feedback mechanism is provided to a current mode differential driver by connecting the center tap of a terminator of the output of the driver through feedback resistors to the gates of a positive and a negative current source connected to the driver. Connecting the center tap between the feedback resistors, the average common mode voltage at the output of the differential driver is substantially constant which avoids variations and reflective noise in high speed data transmission that can occur because of manufacturing tolerances.

Center tap level control for current mode differential driver

A resistance circuit includes an off-chip resistor having a precision resistance; a plurality of on-chip switchable resistors, each of which is capable being switched so as to be coupled in parallel to a nominal resistor; and a resistance comparison unit. The resistance comparison unit compares a plurality of on-chip comparison resistors to the off-chip resistor and couples a number of the on-chip switchable resistors to the nominal resistor so that the combined resistance of the parallel combination of the nominal resistor and the coupled on-chip switchable resistors is within a predetermined range of the precision resistance.

Active trim circuit for CMOS on-chip resistors

An echo cancellation circuit for neutralizing signal reflections in a differential link interface, and a method for achieving the same. The differential link interface includes a line driver that generates a line drive signal and a replica driver for generating a replica signal that mirrors the line drive signal within the differential link. The echo cancellation circuit includes a slope adjustment device within the replica driver for temporarily altering the slope of the replica line drive signal during a signal reflection at the output of the line driver, such that the amplitude of the replica signal corresponds to the amplitude of the line drive signal during the signal reflection.

Echo cancellation circuit for a Bi-directional current mode link

A Complementary Metal Oxide Semiconductor (CMOS) current mode differential link with precompensation is provided. The Complementary Metal Oxide Semiconductor (CMOS) bi-directional current mode differential link with precompensation includes a CMOS driver receiving a data input and having an output coupled to a transmission line. A CMOS replica driver receives the data input and provides a replica driver output substantially equal to the CMOS driver output. A CMOS receiver is coupled to both the transmission line and replica driver output. The CMOS receiver subtracts the replica driver output from a signal at the transmission line. The CMOS driver and the CMOS replica driver include a plurality of parallel current sources. Each of the current sources is arranged to send positive or negative current through a load responsive to an applied control signal. The use of the plurality of parallel current sources allows the CMOS driver to effectively implement precompensation. The output current of the CMOS driver is a function of a data bit and at least one previous data bit.

CMOS bi-directional current mode differential link with precompensation

One phase of a multi-phase spindle motor, normally used to rotate the disk of a disk drive system when power is on, is used to supply power to a capacitor storage circuit when power is lost (turned off or otherwise interrupted). The capacitor storage circuit provides the power to the retract circuit, which retracts the head. The combination of the generator effect of the phase and the capacitor storage circuit provides power to the retract circuit for a time clearly sufficient to reliably retract and lock the head regardless of the bias of the head prior to power loss. Simultaneously with one phase being used to retract the head, the other phases are shorted together to provide regenerative braking. FET drivers, normally used to drive the spindle motor when power is supplied, are used to short out the remaining phases to brake the motor when power is lost. In the preferred embodiment, the capacitor storage circuit is used as a line filter circuit when power is on. Therefore, the major circuit components used for retracting the head and braking the motor upon loss of power (capacitor storage circuit, motor windings, FET drivers) are all used for different purposes when power is on. This efficient use of the same circuitry for multiple purposes results in an efficient, reliable, compact, and relatively inexpensive approach for disk drive head retract and motor braking upon loss of power.

Disk drive head retract and motor braking method and apparatus

A mechanism for moving an access arm carrying a magnetic transducer into the most appropriate position between pairs of consecutive flexible disks in a rotatable disk stack to assure that the proper disk is thereby accessed. The mechanism includes mechanism for preliminarily accessing each of the disks with a plurality of steps between consecutive disks in the stack and filling a position register with a unique identification number from each disk and with numbers of the steps corresponding to each of the disk numbers and mechanism for averaging the step numbers corresponding to each of the disks and placing the average step number in an access table to correspond with each of the disk numbers so that the access arm may be stepped to the step number listed for each of the disks in the access table for a reading or writing action using the transducer.

Flexible disk file access mechanism

A magnetic disk, particularly of the thin flexible type, has a magnetic head traversing the disk in order to come into registry with various concentric tracks on the disk. An electric motor of the stepping type is mechanically connected with the head for so moving the head, and a 'present track number' counter is so electrically connected with the stepping motor as to keep track of the particular magnetic track on which the head is located. On a certain contingency, such as a cessation of power to the system, the circuitry includes components so connected as to cause the stepping motor to move the magnetic head to an outer limit on the disk, outwardly of a prerecorded reference track on the disk. When this point is reached, a switch is actuated by the movement of the head, and connected circuitry causes the head to move back onto the reference track. When a maximum amplitude is detected by the head due to passage over the reference track, the circuitry includes components that reset the content of the 'present track number' counter to zero; and all of the inner tracks within the reference track are counted from the zero count in the 'present track number' counter, so as to thereby compensate for any changes in dimension of the magnetic disk.

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Kenyon, MN, United States of America

Charles C Hanson