Synopsys, Inc.

Charles C Chiang

Subarnarekha Sinha

Qing Su

Xin Wang

Jianfeng Luo

Hui-Ru Jiang

Jamil Kawa

Fan Yang

Jing Guo

Hailong Yao

Yen-Ting Yu

Xuan Zeng

Mathew Koshy

Min-Chun Tsai

Geng-He Lin

Jingyu Xu

Baribrata Biswas

Yongqiang Lu

Beifang Qiu

Ya-Chung Chan

Qiushi Chen

Yen Ting Yu

Xiaoping Hu

Yumin Zhang

A hotspot detection system that classifies a set of hotspot training data into a plurality of hotspot clusters according to their topologies, where the hotspot clusters are associated with different hotspot topologies, and classifies a set of non-hotspot training data into a plurality of non-hotspot clusters according to their topologies, where the non-hotspot clusters are associated with different topologies. The system extracts topological and non-topological critical features from the hotspot clusters and centroids of the non-hotspot clusters. The system also creates a plurality of kernels configured to identify hotspots, where each kernel is constructed using the extracted critical features of the non-hotspot clusters and the extracted critical features from one of the hotspot clusters, and each kernel is configured to identify hotspot topologies different from hotspot topologies that the other kernels are configured to identify.

Lithographic hotspot detection using multiple machine learning kernels

A range-pattern-matching-type DRC-based process hotspot detection is provided that considers edge tolerances and incomplete specification ('don't care') regions in foundry-provided hotspot patterns. First, all possible topological patterns are enumerated for the foundry-provided hotspot pattern. Next, critical topological features are extracted from each pattern topology and converted to critical design rules using Modified Transitive Closure Graphs (MTCGs). Third, the extracted critical design rules are arranged in an order that facilitates searching space reduction techniques, and then the DRC process is sequentially repeated on a user's entire layout pattern for each critical design rule in a first group, then searching space reduction is performed to generate a reduced layout pattern, and then DRC process is performed for all remaining critical design rules using the reduced layout pattern. Candidate locations are then identified using the DRC results, and then the true hotspot locations are confirmed using longest common subsequence and linear scan techniques.

DRC-based hotspot detection considering edge tolerance and incomplete specification

An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2&#xd7;-4&#xd7; computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications.

Distance metric for accurate lithographic hotspot classification using radial and angular functions

A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models. Also, because the cell library can be substantially similar to conventional polynomial-based cell libraries except for the inclusion of preconditioning functions, preconditioning does not significantly increase storage requirements and conventional EDA tools can be readily adapted to use the preconditioned cell library.

Preconditioning for EDA cell library

An accurate process hotspot detection technique based on DRC is provided. In this technique, critical DRC rules can be extracted from a pattern. This extraction can include generating horizontal tiles and vertical tiles in the pattern, and adding directed edges to indicate relations between adjacent tiles in the pattern. Rule rectangles, which can also be generated during the critical DRC rule extraction, describe polygon placement in the pattern with a minimal number of critical DRC rules. The extracted DRC rules can be included in a DRC runset file. DRC can be performed with the DRC runset file on a layout. The DRC results can be filtered using the rule rectangles to identify potential hotspots and to verify actual hotspots.

Accurate process hotspot detection using critical design rule extraction

An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2X-4X computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications.

One embodiment of the present invention provides a system that identifies hotspot areas in a layout. The system receives the layout and a via range pattern which indicates one or more vias and performs range-pattern matching (RPM) on the layout based on a via-free range pattern derived from the via range pattern. The system further identifies at least one candidate area and determines whether via(s) in the candidate area matches the via(s) in the via range pattern. The system can also receives a range pattern with don't care regions. The system determines a core pattern from the range pattern, performs RPM based on the core pattern, and identifies a candidate area. The system then determines whether areas surrounding the candidate area match a non-core effective pattern of the range pattern. The system further determines if the areas surrounding the candidate area satisfy the constraints associated with any vias and the don't care regions.

Range pattern matching for hotspots containing vias and incompletely specified range patterns

A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i.e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout.

Range pattern definition of susceptibility of layout regions to fabrication issues

A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments.

Identifying layout regions susceptible to fabrication issues by using range patterns

Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Fast evaluation of average critical area for IC layouts

One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation.

Method and apparatus for computing dummy feature density for chemical-mechanical polishing

Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points (vertices of the starting polygon having an interior angle greater than 90 degrees), including steps of developing a rectilinear partition tree on at least the I-points of the starting polygon, and using the edges of the partition tree to define the partition of the starting polygon into sub-polygons for mask writing.

Steiner tree based approach for polygon fracturing

One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.

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San Jose, CA, United States of America

Charles C Chiang