International Business Machines Corporation

Charles Brian Hall

Robert J Blainey

Hung Qui Le

Susan Elizabeth Eisen

Cathy May

Harold W Cain

Hua Wang

Bradly George Frey

Reid T Copeland

Peter Wiebe Burka

Roch Georges Archambault

Ali Ijaz Sheikh

Andrew Johnson

Patrick R Doyle

Yan Qi Wang

Peter W Markstein

Nikola Grcevski

Zhong Liang Wang

Zhi Liang

Bradley G Frey

J Kevin O'Brien

Xiao Wei Shen

Yingwei Zhang

A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories

A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Recording and profiling transaction failure source addresses and states of  validity indicator corresponding to addresses of aborted transaction in hardware transactional memories

A system enabling Transactional Memory with overflow prediction mechanism, comprising: prediction unit for predicting the mode for the next execution of a transaction based on the final status of the previous execution of the transaction; execution unit for executing the transaction in the execution mode predicted by the prediction unit, wherein the execution mode comprises overflow mode and non-overflow made. According to this invention, before a transaction is executed, it is predicted whether or not the transaction will overflow, and therefore, the execution of the transaction which is necessary to determine whether or not an overflow will occur is saved.

System enabling transactional memory and prediction-based transaction execution method

Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of branching instructions.

Efficiently emulating computer architecture condition code settings without executing branch instructions

A method for lock reservation using cooperative multithreading is provided. The method includes analyzing code containing async points to support cooperative multithreading. The method also includes identifying a class of code as a candidate for reservation via determining locking properties within the code as a function of locations of async points within the code, and generating reserving code that reserves the shared object when code performing the reservation is considered hot code. The method further includes performing runtime monitoring of reservation performance to detect a contention level for the shared object, and removing the reservation when the runtime monitoring determines that a low level of contention exists. A method for lightweight single reader reserved locks is also provided, including identifying a candidate for reservation containing a read-only locking sequence, conditionally marling the sequence, and generating code using an artificial dependency to control execution order of out-of-line code.

Lock reservation using cooperative multithreading and lightweight single reader reserved locks

An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operatively coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to store a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.

Optimizing source code for iterative execution

This invention provides a process within an optimizing compiler for transforming code to take advantage of update instructions available on some computer architectures. On architectures which implement some form of autoindexing instructions or addressing modes, this process will improve the code generated for looping constructs which manipulate arrays in memory. The process is achieved by selecting memory referencing instructions inside loops for conversion to update forms, modifying those instructions to an update form available on a particular processor, and applying an offset compensation to other memory referencing instructions in the loop so as to enable the program to still address the appropriate locations while using the available autoindexing instructions. The improved compiler and compiler process enables the compiler to convert those program instructions that would otherwise convert to autoindexing instructions not supported by the processor to autoindexing instructions that are supported.

Method for improving the efficiency of arithmetic code generation in an

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Calgary, Canada

Charles Brian Hall