International Business Machines Corporation

Charles B Winn

David W Milton

Tad Jeffrey Wilder

Clarence Rosser Ogilvie

Robert Dov Herzl

Kenneth Anthony Lauricella

Robert Spencer Horton

Paul Mark Schanely

Nitin Sharma

David William Boerstler

Edward B Eichelberger

Gary T Hendrickson

Joseph L Temple, Iii

David T Hui

Richard Frank Rizzolo

Douglas P Nadeau

Peter James Osler

Haluk O Askin

Bijan Salimi

Marc R Turcotte

A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.

Semiconductor layer forming method and structure

A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

Method for identifying and implementing flexible logic block logic for easy engineering changes

A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

Structure for identifying and implementing flexible logic block logic for easy engineering changes

A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.

Minimizing impact of design changes for integrated circuit designs

A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.

Design structure for facilitating engineering changes in integrated circuits

A digital frequency multiplier is provided that continues to adjust its multiplied frequency after the desired multiplied frequency is reached, that can be tested during operation and that is easily scalable. The digital frequency multiplier comprises a frequency detector, a frequency adjuster and a ring oscillator (RO). The frequency detector is configured for receiving a reference frequency and an RO output frequency, and for continuously monitoring a difference between the reference frequency and the RO output frequency. Based on the continuously monitored difference, the frequency detector continuously outputs an adjusting signal to the frequency adjuster. In response thereto, the frequency adjuster outputs selection data to the RO that adjusts the oscillation frequency of the RO, and thus the multiplied frequency of the digital frequency multiplier. Testable and growable logic circuitry are provided within the RO that allow the digital frequency multiplier to be tested during operation and easily scaled.

Digital frequency multiplier

An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.

Method and apparatus for verifying timing rules for an integrated

A level shifting circuit operating at low power with minimal signal delays. The circuit employs high capacitance diodes to shift signals from a first signal level to a second higher or lower signal level. The capacitance is obtained by either providing a discrete capacitor shunt across the diode or by using diode connected transistors. Diode connected transistors are biased to provide the necessary capacitance. A pair of high capacitance diode level shifters is used as a differential pair level shifter by connecting the reference resistors to a common reference potential.

Speed enhanced level shifting circuit utilizing diode capacitance

A low signal margin detect circuit for detecting reduced signal levels in differential current switch (DCS) or current switch emitter follower (CSEF) circuits. The circuit is connected to the outputs of a DCS circuit or to the output of a current switch emitter follower circuit and a reference voltage. A signal difference between the inputs is determined and, if less than an established amount, an error signal is generated. The detect circuit is enabled by a TESTBIAS signal. Two error signals are developed, ERRORX and ERRORY, which can be dotted with the error signals from adjacent circuits in the X and Y directions. This enables detection of the failing circuit through the use of appropriate error signal detection devices.

Low signal margin detect circuit

An output stage device for an enhanced differential current switch. The output stage receives a differential signal pair from a prior logic stage and must shift the output signals to the levels necessary for the next stage. The output stage has a differential pair of emitter followers that are capacitively cross coupled. Capacitors couple the collector of a first transistor to the emitter of the second. The capacitors can be formed from forward biased diodes or transistors. The result is a more rapid falling output transition while reducing power requirements.

Capacitively cross-coupled DCS emitter-follower output stage

An improved differential cascode current push-pull driver is provided by controlling the up level by clamping the collector node with respect to output signal reference VR to less than VCC. The collector resistors are made smaller so there is smaller signal swing and faster operation.

Fast limited swing push-pull driver

A compensating upshift circuit providing low signal degradation and operating at high speed and at low power. Capacitor shunted diodes cross-couple the collectors and bases of two transistors. The cross-coupling eliminates signal swing degradation in the upshift circuit and controls current through the two collector resistors. Equalized collector resistor current eliminates signal swing degradation while providing an upshift circuit with short delays. The capacitor shunted diodes can be replaced by diode connected transistors configured to provide the necessary collector-base capacitance.

Enhanced differential current switch compensating upshift circuit

This invention reduces the Delta I noise on an integrated circuit chip by reducing the changes in current supply required for transitions in logic states of the input/output devices. The invention uses a 3/6 binary code for communicating between integrated circuit chips. This code uses six bits to represent the 16 hex code digits typically used for computer instructions. Three of the six bits are in a high logic state and three of the six bits are in a low logic state for all 16 hex code representations. Therefore, changing from any one logic state to another, does not change the overall current supply required by the six input/output devices. Groups of six input/output devices (corresponding to the 3/6 code) are located relatively close to each other with respect to the power supply pins which supply current to the six input/output devices. As a result, there is a high to low transition for every low to high transition over similar parasitic impedances on the input/output devices. This leads to low Delta I noise because the noise created by individual transitions cancel each other out when viewed as a six device group. The high overhead pin count for a six digit code instead of the normal four digit code for hex representation is compensated for because input/output pins normally replaced by extra power supply pins (to reduce Delta I noise) can be used as input/output pins. Therefore, the 3/6 code frees up extra input/output pins when the Delta I noise would normally force those pins to be used for power supply.

Growing community of inventors

Colchester, VT, United States of America

Charles B Winn