Srx Corporation

Data General Corporation

Mostek Corporation

Charles B Johnson

David B Hildebrand

Jeffrey L Box

Ian A Young

Howard D Gardener

A distributed switching system (20) is provided for implementation in an integrated circuit utilizing a switching bus (30) in which bus lines (30a-30n) are time division multiplexed serial data streams consisting of time slots used for both transmit and receive directions. The bus lines (30a-30n) comprise a single bi-directional bus used for both inter-processor communication and for transparent voice and data switching. The distributed switching system (20) includes a bus line selector (31) to select one of the plurality of bus lines (30n-30n) to perform space switching functions. A slot counter (32) is provided for selecting one of a plurality of time slots on the plurality of bus lines (30n-30n) to perform a time switching function. Interface shift registers (33, 35) are interconnected for transmitting to and receiving data from the switching bus (30). Interconnected to the bus registers (33, 35) is a line interface register (34) for transmitting to and receiving data from a digital instrument.

Distributed switching system

A distributed switching system (20) is provided for implementation in an integrated circuit utilizing a switching bus (30) in which bus lines (30a-30n) are time division multiplexed serial data streams consisting of time slots used for both transmit and receive directions. The distributed switching system (20) includes a bus line selector (31) to select one of the plurality of bus lines (30a-30n) to perform space switching functions. A slot counter (32) is provided for selecting one of a plurality of time slots on the plurality of bus lines (30a-30n) to perform a time switching function. Interface shift registers (33, 35) are interconnected for transmitting to and receiving data from the switching bus (30). Interconnected to the bus registers (33, 35) is a line interface register (34) for transmitting to and receiving data from a digital instrument.

Apparatus 117 interfaces system multiplexing/demultiplexing (MUX/DMUX) station circuitry 113, which exchanges pulse code modulated (PCM) signal samples of voice, data and control information in an interleaved port group format with a plurality of the system user ports 120 in each of a succession of sample time intervals, with the system time slot interchange (TSI) matrix 110 which switches the PCM voice, data and control signal samples in each sample time interval in groups of common signal type.

PCM channel multiplexer/demultiplexer

A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.

Growing community of inventors

Dallas, TX, United States of America

Charles B Johnson