Texas Instruments Corporation

Texas Systems Incorporated

Charles Anthony Odegard

Vinu Yamunan

Marvin Wayne Cowens

Masood Murtuza

Phillip R Coffman

Tz-Cheng Chiu

Mohammad Yunus

Ferdinand Borromeo Arabe

Willmar E Subido

Jaimal Mallory Williamson

Roger J Stierman

Rebecca Lynn Holdford

A packaged semiconductor device () comprising a semiconductor chip () of an area having a first surface () including a plurality of bond pads () linearly arrayed, adjacent pads having a first pitch () center-to-center; an insulating layer () on the first chip surface covering the chip area, the layer having a height () and a second surface () parallel to the first surface; the second surface including contact nodes () in staggered array, the nodes having the same plurality as the pads, adjacent nodes having a second pitch () center-to-center greater than the first pitch; and metal wires through the layer height connecting the pads to respective nodes.

Wire-based methodology of widening the pitch of semiconductor chip terminals

In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of separator pedestals disposed between a first face of a die and a second face of a substrate, the substrate positioned generally parallel with, and spaced apart from, the die, and the first face being opposite the second face. The plurality of separator pedestals are operable to selectively force the die and substrate apart, increasing the stand-off height of the flip chip assembly.

System and method to increase die stand-off height

A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Patterned plasma treatment to improve distribution of underfill material

A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Adhesion by plasma conditioning of semiconductor chip

Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the die during heating of the solder to a liquescent state, thereby increasing the stand-off height of the die above the substrate. The lifting force is maintained during cooling of the solder to a solid state, thereby forming increased stand-off height solder connections.

Increased stand-off height integrated circuit assemblies, systems, and methods

A system () for manufacturing product, in which a first work station () is operable to perform a first manufacturing action on the product parts; this first station has a first entrance () and a first exit). A second work station () is operable to perform a second manufacturing action on the product parts; this second station has a second entrance () and a second exit (). A transport line () between the first exit and the second entrance is operable to move the product parts under computer control. A chamber () encloses a portion of the line and is constructed so that the transport achieves a balanced throughput from the first station to the second station, while the product parts are exposed to computer-controlled environmental conditions () during transport through the chamber. The balanced throughput in the chamber is achieved by waiting lines for the product with computer-controlled monitors () for product parts' positions and times in the chamber.

Manufacturing system and apparatus for balanced product flow with application to low-stress underfilling of flip-chip electronic devices

Adhesion by plasma conditioning of semiconductor chip surfaces

A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less than 180 &#x3bc;m. A metallic bump of reflowable metal is attached to each of these contact pads. The assembly further has an electrically insulating substrate with a second plurality of metallic terminal pads in locations matching the locations of the contact pads. Each of the bumps also attached to these matching terminal pads, respectively, whereby the chip is interconnected with the substrate spaced apart by a gap. An adherent polymeric encapsulant fills the gap so that the encapsulant is free of voids. It is a pivotal feature in the method that vibration energy, up to ultrasonic frequencies, is used while the encapsulant is still in a low-viscosity precursor state in order to ensure the void-free spreading of the precursor throughout the gap between chip and substrate. The vibration energy ensures uniform underfill distribution even when the gap and the bump pitch are narrow, with uniform distribution of any fillers, and enhanced adhesion to chip, substrate and bumps.

Vibration-assisted method for underfilling flip-chip electronic devices

A probe having a built-in reference plane for use with TDR testing includes a conductive sheet member such as a wire mesh which is attached to a ground input of a TDR system. The conductive sheet is located proximate the tip of the test probe and extends radially from an axis of the test probe thereby providing its own reference ground plane.

Growing community of inventors

McKinney, TX, United States of America

Charles Anthony Odegard