International Business Machines Corporation

Charles Andrew McLaughlin

Alongkorn Kitamorn

Robert Kimberlin Foster

Douglas Craig Bossen

David R Willoughby

George Henry Ahrens, Jr

Christine Iju Wang

Casey Lee McCreary

Steven Mark Thurber

Danny Marvin Neal

Van Hoa Lee

John Steven Langford

Ajay Kumar Mahajan

Mike Conrad Duron

Robert Allan Faust

Michael Thomas Vaden

James O Nicholson

John Thomas O'Quin, Ii

Kanisha Patel

Stephen Joseph Schwinn

Jayeshkumar M Patel

Kurt Paul Szabo

Craig Henry Shempert

Walter Manfred Lipp

Chet Mehta

Sayileela Nulu

Donald LeRoy Thorson

Joy Mei-Jen Underhill

Hemlata N Reddy

Andrew G Derr

Alongkron Kitamorn

Camvan Thi Nguyen

Generally speaking, systems, methods and media for detection and network reconfiguration upon changes in dynamic host configuration protocol (DHCP) IP addresses are disclosed. Embodiments of a method may include setting a renew time and a rebind time of a DHCP configuration and establishing an IP address with a first DHCP server. Embodiments may also include, after passage of the renew time, transmitting a renew request to the first DHCP server at its IP address and, in response to failure to receive an acknowledgement message from the first DHCP server, determining if the first DHCP server IP address is still valid. Embodiments may also include, in response to determining that the first DHCP server IP address is not still valid, retrieving a second, different DHCP server IP address from a network change event signal and configuring a network adapter based on the second DHCP server IP address.

Automatic network reconfiguration upon changes in DHCP IP addresses

A method, system, and computer program product are disclosed for managing an application's persistent data across multiple different release versions of the application. A format for a memory area is defined wherein the persistent data will be stored according to a first release version of the application. The format is organized to permit the application running at different release versions to access the memory area. The memory area is accessed using the application that is running at a second release version. The memory area is divided into individually accessible sections. The format includes a template file for each section for each release version.

Method, system, and computer program product for managing persistent data across different releases

The present invention provides a method, apparatus, and computer instructions for recovering an image of partition configuration information data for a set of partitions having at least one affinity partition in a logical partition data processing system. (Damage to an image of partition configuration data is detected. Current partition data is compared with a backup partition data. A merger of the current partition configuration data is made with the backup logical partition data if a conflict is present between the current partition configuration data and the backup partition data. The merger is performed in a manner avoiding stopping an operation on a running partition in the set of partitions.

Method and apparatus for recovering logical partition configuration data

The present invention provides a method, apparatus, and computer implemented instructions for managing a set of objects for a plurality of terminals. The set of objects are stored in a memory, such as a nonvolatile random access memory in a data processing system. The set of objects are used to configure logical partitions within the data processing system. Access to the set of objects is provided to the plurality of terminals through a service processor.

Method and apparatus for maintaining profiles for terminals in a configurable data processing system

A method, apparatus, and computer implemented instructions for providing a plurality of terminals access to a service processor located within the data processing system. A first indication is returned if the service processor is unlocked in response to receiving a request from a terminal to provide a terminal within the plurality of terminals sole access to access the service processor. The service processor is locked to provide the terminal sole access to service processor in response to receiving a request to provide a terminal sole access to access the service processor. In response to receiving a request to provide a terminal sole access to access the service processor, a second indication is returned if the service processor is locked.

Method and apparatus for managing access to a service processor

A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.

Method and apparatus for verifying hardware implementation of a processor architecture in a logically partitioned data processing system

A mechanism is provided for predicting cache array bit line or driver failures. This mechanism checks for five consecutive errors at different addresses within the same syndrome on invocation of event scan polling to characterize the failure. Once the failure is characterized, it is reported to the system for corrective maintenance including dynamic and/or boot time processor deconfiguration or preventive processor replacement.

Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures

A method and apparatus for simulated error injection for processor deconfiguration design verification is provided. A simulated error condition request is received from a user through software, such as the operating system executing in the multiprocessor data processing system. In response to the requested simulated error condition, an error condition is injected into a processor of the multiprocessor data processing system via instruction execution. In response to the detection of the error condition and execution of error-path code, a processor is deconfigured. The error condition may be injected by executing an instruction to set an error condition bit in an error condition register.

Method and apparatus for simulated error injection for processor deconfiguration design verification

Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O devices communicating via the bus, includes categorizing, in a recursive manner, the I/O subsystem, and isolating a source of an error condition within the I/O subsystem. Further, the I/O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input/output mechanism, coupled to the processing mechanism, comprising a plurality of input/output devices and bridges coupled to a PCI bus and communicating according to a PCI standard. In addition, the system includes a fault isolation mechanism within the processing mechanism for identifying a source of an error condition in the input/output mechanism. Further, the fault isolation mechanism performs categorization of the input/output mechanism in a recursive manner.

Method and system for fault isolation for PCI bus errors

A method and apparatus in a multiprocessor data processing system for managing a plurality of processors. Monitoring for recoverable errors in a set of processors is performed. Responsive to detecting a recoverable error for a processor in the set of processors, a determination is made as to whether the recoverable error indicates a trend towards an unrecoverable error. Responsive to a determination that the recoverable error indicates a trend towards an unrecoverable error, actions are initiated to stop the processor.

Method and apparatus for run-time deconfiguration of a processor in a symmetrical multi-processing system

Method and system aspects for check stop error handling are provided. A method aspect for check stop error handling in a computer system, the computer system comprising a plurality of components including a processor that supports an operating system and firmware, includes utilizing a service processor following a check stop error for error data retrieval and attempting a reboot of the computer system. The method further includes initiating firmware for failure reporting based on the error data retrieval when the reboot is successful.

Method and system for check stop error handling

Aspects for detecting environmental faults in redundant components of a computer system are described. In an exemplary method aspect, the method includes monitoring system environment conditions, including a status for redundant power supply and cooling components. The method further includes registering a failure condition with an appropriate error type when a monitored system environment condition exceeds a design threshold, and utilizing the registered failure condition as data in an architected error log.

Environmental and power error handling extension and analysis for systems with redundant components

In accordance with the method and system of the present invention, a local processor utilizes registers arranged in a fault/mask/cache fashion for environmental control and sensing within a data processing system. The local processor continuously reads input data from a variety of environmental sensors in order to determine if a threshold level has been reached and a fault condition exists. Cache registers allow the local processor to store/pass detailed sensor information to system firmware within system processor(s). The local processor sets a fault bit within a fault register designed to cause an interrupt to the system level firmware if any of its bits are non-zero, indicating that a fault condition has occurred. A mask register is designed to allow the interaction of both the local processor and system processor(s) when an interrupt is being serviced and help keeps track of which interrupts are being serviced and which are yet to be serviced in the case of multiple interrupt sources. The system firmware will service the interrupt and set the mask bit. The action will signal the local processor that the system has acknowledged the interrupt and will take the appropriate action. The local processor may now post another fault, exactly like the first fault, by clearing the mask bit and causing a subsequent interrupt to the system. The fault, mask, cache, and both local and system processor(s) work together to provide a positive interlock for synchronizing their actions with each other.

Method and system for environmental sensing and control within a computer system

A method and system for deconfiguring software in a processing system is disclosed. In one aspect, a processing system comprises a central processing unit (CPU), and a memory coupled to the CPU. The memory includes a memory array and a memory controller for capturing information concerning the status of the memory array. The processing system includes a service processor for gathering and analyzing status information from the memory controller. The processing system also includes a nonvolatile device coupled to the CPU and the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the memory array from the service processor. The deconfiguration area also provides information for deconfiguring at least a portion of the memory array during a boot time of the processing system. Accordingly, through the present invention, memory errors are detected during normal computer operations by error detection logic. This detection is utilized during any subsequent boot process by service processor and CPU boot firmware to deallocate the defective memory module. This is accomplished through the use of error status registers within the memory controller and through the use of a deconfiguration area in the nonvolatile device which provides information directly to the CPU boot firmware.

Method and system for boot-time deconfiguration of a memory in a processing system

A method and system for deconfiguring a CPU in a processing system is disclosed. In one aspect, a processing system is disclosed that comprises a central processing unit (CPU), and a memory coupled to the CPU. The error status register for capturing information concerning the status of the CPU. The processing system includes a service processor for gathering and analyzing status information from the CPU error register. The processing system also includes a nonvolatile device coupled to the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the CPU from the service processor. The deconfiguration area also provides information for deconfiguring a CPU during a boot time of the processing system. Accordingly, through the present invention, CPU errors are detected during normal computer operations by error detection logic. This detection is utilized during any subsequent boot process by service processor firmware to deallocate the defective CPU. This is accomplished through the use of error status registers within the CPU and through the use of a deconfiguration area in the nonvolatile device which provides information directly to the service processor.

Growing community of inventors

Round Rock, TX, United States of America

Charles Andrew McLaughlin