Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.v.

Huawei Technologies Duesseldorf Gmbh

Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.v.

Charles-Alix Manier

Hans-Hermann Oppermann

Kai Zoschke

Tolga Tekin

Martin Wilke

Juliane Fröhlich

Robert Gernhardt

Disclosed herein is a method for manufacturing a semiconductor comprising mechanically connecting one or more separate semiconductor components to a common intermediate carrier, arranging the intermediate carrier with respect to a substrate so that, at least for a majority of the semiconductor components, at least one solder pad of a particular semiconductor component lies opposite a solder pad of the substrate associated therewith forming a solder joint, and connecting mutually associated solder pads of the one or more semiconductor components and the substrate by melting and solidifying a solder material arranged between the mutually associated solder pads. A surface tension of the solder material between the mutually associated solder pads of the substrate and the one or more semiconductor components sets a predetermined position of the intermediate carrier relative to the substrate, in which the one or more semiconductor components assume a target position relative to the substrate.

Method for manufacturing a semiconductor arrangement

A method for manufacturing a device is provided. The method comprises providing a first carrier having attached thereto a plurality of chips by means of an adhesive layer of the first carrier, a first surface of the plurality of chips being attached to the first carrier. Further, the method comprises selectively attaching a second surface of a subset of the plurality of chips to a conveyor carrier by means of a structured adhesive layer of the conveyor layer. Further, the method comprises selectively releasing the subset of the plurality of chips from the first carrier by means of debonding corresponding sections of the adhesive layer of the first carrier. Further, the method comprises attaching the first surface of the subset of the plurality of chips to a substrate of the device.

Massive parallel assembly method

Disclosed herein is an optical system, comprising a first optical component, featuring a first waveguide and a recess which passes at least partially through the first optical component from a front side to a back side, a second optical component, arranged in the recess of the first optical component, and a second waveguide optically coupled with the first waveguide, and a carrier substrate. The first optical component including a first marking set with a defined position/orientation relative to the first waveguide, the second optical component including a second marking set with a defined position/orientation relative to the second waveguide, and based on a relative position/orientation of the first and second marking sets, determine whether the first and the second optical components are aligned in a reference plane that is parallel to a surface of the carrier substrate, such that the first and the second waveguide are optically coupled.

Optical system, optical components, and method for manufacturing an optical system

Disclosed is a system for and a method of manufacturing of an optical system, including a first optical component, comprising a first waveguide and a carrier substrate, wherein the first optical component is arranged on the carrier substrate. The first optical component comprises a first markup set having a defined position/orientation with respect to the first waveguide, the carrier substrate has a second markup set detectable based on a relative position/orientation of the first and second markup sets when a desired orientation of the first waveguide relative to the carrier substrate is achieved in a reference plane extending parallel to a surface of the carrier substrate.

Markup system for optical system, carrier substrate, and method for manufacturing of same

A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.

Growing community of inventors

Berlin, Germany

Charles-Alix Manier