Ami Semiconductor, Inc.

Semiconductor Components Industries, LLC

American Microsystems, Inc.

Charles A Edmondson

Brian R Kauffmann

James Robert Brown

Timothy G O'Shaughnessy

Joseph J Walsh

Morgan K Ercanbrack

Timothy Derosier

A level-shifter circuit capable of operating at low voltages. Two complementary current paths are provided between each of two intermediate nodes (at least one of which being an output node) and one of the supply voltages. A network of field-effect transistors are coupled between the other voltage supply and the intermediate nodes. The transistors include a pull-up (or pull-down as the case may be) transistor pair coupled to the high (or low as the case may be) voltage supply. There are two cascode transistor pairs coupled between the pull-up (or down) transistors and the corresponding intermediate node. One cascode pair couples the respective intermediate node to the drain terminal of the respective pull-up (or down) transistor. The other cascoded pair cross-couples the intermediate node to the gate terminal of the opposite pull-up (or down) transistor.

Level shifting using cross-coupled cascode transistors

Systems and methods are disclosed for distributing memory within one or more regions of circuitry that perform logic functions (or other types of functions that require dense interconnect structures) on an integrated circuit. The distributed memory reduces high density routing congestion, allows increased logic utilization, and provides areas for additional interconnect structure. Various techniques are also disclosed for accessing the memory.

Distributed memory and logic circuits

An SRAM memory includes a pull-up device coupled to each row of word lines in an array of SRAM cells. The pull-up devices are sized such that when a row is selected, the time for the associated word line to fully charge is sufficiently slow such that data stored in the selected SRAM cells are not corrupted during a read operation. By slowly charging the word lines, the corresponding access transistors are also slowly turned on, resulting in the coupled bit lines slowly charging or discharging from the data stored in the SRAM cell. Because there is not a sudden large charge transfer between the stored data and the coupled bit line, the data will not be corrupted during a read operation, and read precharge circuitry is not required.

Static random access memory (SRAM) without precharge circuitry

A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator. The frequency converter has a highly linear transfer function which is established by the resolution of a frequency counter. For example, a transfer function having approximately 0.1% accuracy in linearity is achieved using a 10-bit resolution frequency counter. Using indirect frequency synthesis, the controlled oscillator generates precisely controlled timing signals.

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Pocatello, ID, United States of America

Charles A Edmondson