Hewlett-packard Company

Agilent Technologies, Inc.

Hewlett-packard Corporation

Charles A Brown

Billy E Thayer

Charles E Moore

Donald M Reid

Steven Kalata

Rajeev Badyal

Robert B Manley

Damir Smitlener

Jay D McDougal

George C Reick

George C Rleck

Don R Wiseman

The present invention teaches an apparatus for testing the circuitry in an input/output (I/O) pad without probing the contact site on the I/O pad. A dominant driving circuit has an output coupled to a first contact site on a semiconductor chip. A subordinate driving circuit also has an output coupled to the first contact site on the semiconductor chip. A test control circuit sets a drive fight up between the dominant and subordinate driving circuits, the test control circuit selecting a stronger drive strength for the dominant driving circuit than for the subordinate driving circuit. The drive fight produces a test value at the first contact site. The test value from the first contact site is transferred to a second contact site on the semiconductor chip to be probed by an external prober.

Self-testing input/output pad

An application-specific integrated circuit (ASIC) with a CPU module and a memory module connected to the CPU. The memory has a size selected from a set of alternative memory sizes. The CPU has a memory interface device having an output connected to the memory, and includes a memory test device connected to the memory. The memory test device has a size selector input that receives a memory size code, so that the memory test device is operable to test a memory module of any of the alternative memory sizes in response to alternative memory size codes received on the size selector input. The memory may be RAM or ROM, and the size codes may correspond to address size data stored in the memory test device.

Integrated circuit having memory built-in self test (BIST) for different

IDDQ of an integrated circuit is rapidly measured with system test equipment providing sampled pass/fail outputs. A switch couples the power supply to the integrated circuit and another switch returns a sense signal input to the integrated circuit such that the power may be interrupted to measure the decay of the voltage across the integrated circuit. A monitor signal output is coupled to the integrated circuit to enable monitoring of the voltage decay. At least one processor, which periodically samples the voltage signal, compares the magnitude of the voltage signal at the time of each said periodic sample to a predetermined reference signal, indicates a voltage signal less than the reference signal and calculates the IDDQ based upon the number of periodic samples from the time power is removed from the integrated circuit and the voltage of the reference signal.

Method and apparatus for determining IDDQ

In order to measure IDDQ in a large integrated circuit, multiple IDDQ monitors sampling the current drawn by selected portions of the circuit are placed on the integrated circuit chip. The output of each IDDQ monitor is combined and supplied to one output port when any of the IDDQ monitors detect current in excess of a predetermined threshold. The output of each IDDQ monitor is also stored in a memory for subsequent readout at a second output port for detection of particular portions drawing the excessive current.

Multiple on-chip IDDQ monitors

A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs. A photolithographic mask embodying a configurable circuit is provided to a designer who utilizes a CAD program to lay down polysilicon connections to select the drive transistors and disable the nonselected transistors.

Method of making a CMOS output pad driver with variable drive currents,

CMOS output pad driver with variable drive currents ESD protection and

Multiple punchthru devices are coupled between multiple metal-two conductors and a metal-one bond pad. Each punchthru device has the capacity to couple its respective metal-two conductor to the bond pad when a predetermined voltage potential exists between the metal-two conductor and the bond pad. A set of metal-one islands, one set associated with each metal-one bond pad cell, resides in a bond pad channel. The positioning of the punchthru devices and the islands minimizing the bond pad cell size and minimizing the spacing between adjacent bond pad cells. The bond pad cell configuration also allows any metal-two conductor to be coupled to the bond pad without having to rearrange punchthru devices or reconfigure the bond pad cell. The multiple punchthru devices associated with each bond pad cell provide redundant overvoltage protection superior to present overvoltage protection circuits.

Punchthru ESD device along centerline of power pad

An integrated current generator circuit operates in conjunction with a known reference voltage and internal and external reference resistances. The current generator circuit includes three operational modes. In the first operational mode, the reference voltage is impressed upon the internal reference resistance to generate one or more relatively inaccurate output currents. In a second operational mode, the reference voltage is impressed upon an external reference resistance to generate one or more highly accurate output currents, even if an internal ESD resistor is used, or if the bonding pad has high series parasitic resistance. An alternative voltage sensing path is included to ensure the accuracy of the reference current. In a third operational mode, the reference voltage is again impressed upon the internal resistance, with the corresponding node voltage being connected to an external integrated circuit bonding pad.

Precision reference current generator

A programmable power supply for driving LEDS is disclosed that includes a reference current leg and a number of output current legs. Both the reference current leg and the output current legs are further comprised of a plurality of parallel driver FET-control FET pairs, in which the driver and control FETs are connected in series. The driver FETs are biased by a reference voltage that provides a predetermined maximum output current. The control FETs are individually selected to provide a controlled output current. The individual control voltage is either a positive voltage, which disables the control FET, or a predetermined cascode voltage that places the control FET at or into the high output impedance saturation conduction region. By placing the control FETs into the saturation region, the output current is substantially insensitive to voltage fluctuations at the output

Light-emitting diode array current power supply including switched

An apparatus and method is disclosed for minimizing the loading effect of the feedback network on the output voltage of an op-amp circuit. A single current source is coupled to the output of the op-amp to provide a predetermined current. By properly selecting the current source to be equal to the current demanded by the feedback network, the output current of the op-amp is significantly reduced. In turn, the loading effects of the feedback network resistors on the op-amp are significantly reduced and the accuracy of the op-amp circuit gain is improved.

Current compensation technique for an operational amplifier

A power supply circuit for an LED print head has a reference current source connected to a printer system reference voltage for providing a second reference voltage for an individual, integrated circuit chip. The reference current source is controlled by an operational amplifier, the output of which comprises the second reference voltage. A plurality of output driver FETs are biased by the reference voltage. Each output driver FET provides current to an associated LED responsive to a data signal. A plurality of control FETs are connected in parallel with each other and in series with each output driver FET for varying the LED output current responsive to programming data signals. A second group of control FETs is interposed in the feedback loop of the operational amplifier for varying the second reference voltage responsive to a different set of programming data signals.

Light emitting diode array current power supply

A power supply circuit for an LED print head has a reference current source connected to a printer system reference voltage for providing a second reference voltage for an individual, integrated circuit chip. A plurality of substantially similar field effect transistors have their gates connected to the chip reference voltage for providing substantially similar current to each of a plurality of light emitting diodes. The current is enabled to each such LED by the presence or absence of a data signal. A reference resistor in the reference current source permits adjustment so that each of a plurality of integrated circuit chips can provide substantially similar current to each of a plurality of LED dice, or adjust the current level, if required, to achieve similar light output from each LED.

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Corvallis, OR, United States of America

Charles A Brown