Apple Inc.

Amazon Technologies, Inc.

Charan Srinivasan

Eyal Gurgi

Matthew John Byom

Andrew W Vogan

Nafea Bshara

To improve the reliability of a memory system, data and error correction codes associated with the data can be stored in a first memory. Parity bits calculated over data bits in the first memory can be stored in a second memory. The parity bits in the second memory can be used to recover errors that are uncorrectable by the error correction codes. The first memory can be implemented, for example, using an emerging memory technology, while the second memory can be implement using a different memory technology.

Reliability improvements for memory technologies

A storage system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells coupled to multiple Bit Lines (BLs). The memory cells are programmed and read in sub-groups of multiple BLs, and the sub-groups correspond to respective addresses. The storage circuitry is configured to generate a sequence of addresses for reading memory cells that together store a data part and a pattern part containing a predefined pattern, via multiple respective sub-groups, to detect that the data part read from the memory cells is erroneous due to a fault that occurred in the sequence of addresses by identifying a mismatch between the pattern part read from the memory cells and the predefined pattern, and, in response to detecting the fault, to take a corrective measure to recover an error-free version of the data part.

Recovering from addressing fault in a non-volatile memory

An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory that includes multiple memory cells arranged in multiple planes that each includes one or more blocks of the memory cells. The storage circuitry is configured to apply a multi-plane storage operation to multiple blocks simultaneously across the respective planes. In response to detecting that the multi-plane storage operation has failed, the storage circuitry is configured to apply a single-plane storage operation to one or more of the blocks that were accessed in the multi-plane storage operation, including a given block, and to identify the given block as a bad block if the single-plane operation applied to the given block fails. The storage circuitry is further configured to store data in the blocks that were accessed in the multi-plane operation but were not identified as bad blocks.

Identifying a failing group of memory cells in a multi-plane storage operation

A method for data storage includes preparing first data having a first size for storage in a memory device that stores data having a nominal size larger than the first size, by programming a group of memory cells to multiple predefined levels using a one-pass program-and-verify scheme. The first data is combined with dummy data to produce first combined data having the nominal size, and is sent to the memory device for storage in the group. The dummy data is chosen to limit the levels to which the memory cells in the group are programmed to a partial subset of the predefined levels. In response to identifying second data to be stored in the group, the second data is combined with the first data to obtain second combined data having the nominal size, and is sent to the memory device for storage, in place, in the group.

One-pass programming in a multi-level nonvolatile memory device with improved write amplification

Systems and methods for managing data in non-volatile memory devices across a large range of operating temperatures are provided. Embodiments discussed herein selectively reprogram previously programmed data at a temperature that better enables the data to be read regardless of where within the range of operating temperatures the data is being read. Circuitry and methods discussed herein can keep track of a program temperature associated with each portion of non-volatile memory and use this information along with other criteria to selectively perform temperature based moves of data. This enables a mechanism for data to programmed in out-of-bounds temperature ranges to be reprogrammed within an in-bounds temperatures range so that a temperature delta between the reprogrammed temperature and the read operation temperature is below a threshold that ensure efficient and error free read operations to be performed.

Systems and methods for managing non-volatile memory based on temperature

A storage device includes multiple memory cells and storage circuitry. The storage circuitry is configured to write data to a group of the memory cells by applying to the group of the memory cells up to a maximal number of programming pulses. The storage circuitry is further configured to evaluate, after applying less than the maximal number of programming pulses, a criterion that predicts whether or not the data will be written successfully within the maximal number of programming pulses, and when the criterion predicts that writing the data will fail, to perform a corrective operation.

Early prediction of failure in programming a nonvolatile memory

A method includes, in a memory block, which includes at least a string of memory cells that is selectable using at least a select transistor, sensing a current flowing through the string. A failure in the memory block, which causes the string to conduct even when unselected using the select transistor, is detected based on the sensed current. A corrective action is initiated in response to the identified failure.

Detection and localization of failures in 3D NAND flash memory

A method for data storage includes setting a plurality of memory cells to hold respective target analog values, by applying to the memory cells a sequence of iterations, each iteration includes attempting to set the target analog values and then verifying whether the target analog values have been reached in accordance with a verification condition. After applying a predefined number of the iterations, the verification condition is relaxed and a condition of whether the target analog values have been reached in accordance with the relaxed verification condition is verified.

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San Jose, CA, United States of America

Charan Srinivasan