International Business Machines Corporation

Koninklijke Philips Corporation N.v.

Globalfoundries Inc.

Other

Charalampos Pozidis

Nikolaos Papandreou

Roman Alexander Pletka

Nikolas Ioannou

Thomas P Parnell

Thomas Mittelholzer

Timothy J Fisher

Aaron Daniel Fry

Sasa Tomic

Evangelos Stavros Eleftheriou

Radu Ioan Stoica

Abu Sebastian

Charles John Camp

Milos Stanisavljevic

Andrew Dale Walls

Tobias Blaettler

Ioannis Koltsidas

Angeliki Pantazi

Sri Muthuthamby Sri-Jayantha

Theodore Antonakopoulos

Mark Alfred Lantz

Giovanni Cherubini

Hien Phu Dang

Arun Sharma

Deepak Ranjan Sahoo

Celestine Duenner

Thomas R Albrecht

Ajay Dholakia

Andreea Anghel

Gary A Tressler

Daniel Frank Moertl

Robert Edward Galbraith

Jan Van Lunteren

Damir Anthony Jamsek

Andrew Kenneth Martin

Venkataraman Kartik

Dimitrios Sarigiannis

Giovanni Cherubinni

Gerd K Binnig

Michel Despont

Peter Vettiger

Michail Vlachos

Kubilay Atasu

Daniele Caimi

Johannes Wilhelmus Maria Bergmans

Steven Paul Norgaard

Antonios Kornilios Kourtis

Jeremy T Ekman

Vasileios Vasileiadis

Christophe P Rossel

Gerald Mark Grabowski

Abby Harrison

Thomas Albrecht

Urs Frey

Chung H Lam

Urs T Duerig

Robert Haas

Mircea R Gusat

Armin W Knoll

Adalberto Guillermo Yanes

Christoph Hermann Hagleitner

Walter Haeberle

Brent William Yardley

Thomas D Weigold

Willem Marie Julia Marcel Coene

SangBum Kim

Thomas J Griffin

Kevin E Sallese

M Dean Sciacca

Daniel Krebs

Martin Petermann

Cesar Berrospi Ramis

Gian R Salis

Peter Baechtold

Mussie T Negussie

Evangelos Elftheriou

Reza S Moheimani

Celestine Mendler-Duenner

Serge Monney

Jenny L Brown

Jianjiang Wang

Lili Lyubchova Georgieva

Malgorzata Lazuka

Matt Reuter

Michael Despont

Abu Sabastian

Maria Varsamou

The invention is notably directed to a computer-implemented method, which aims at jointly identifying an optimal source of computerized resources and optimizing a configuration of the computerized resources. The method comprises configuring a Best-Arm Identification algorithm, in order to (i) associate arms of the algorithm with respective sources of computerized resources and (ii) connect the arms to one or more optimizers. Each of the optimizers is designed to optimize a configuration of such computerized resources. Next, the method iteratively executes the Best-Arm Identification algorithm to progressively eliminate the sources, with a view to eventually identifying one of the sources as an optimal source with an optimized configuration. Several iterations are accordingly performed. During each iteration, each of the arms is pulled and the rewards earned by pulling the arms are computed. Pulling each arm causes to optimize a configuration of computerized resources of a respectively associated source.

Configuration and optimization of a source of computerized resources

A method of dynamically optimizing decision tree inference is provided. The method, which is performed at the computerized system, repeatedly executes one or more decision trees for inference purposes and repeatedly performs an optimization procedure according to two-phase cycles. Each cycle includes two alternating phases, i.e., a first phase followed by a second phase. The decision trees are executed based on a reference data structure, whereby attributes of nodes of the decision trees are repeatedly accessed from the reference data structure during the first phase of each of the cycles. First, the accessed attributes are monitored during the first phase of each cycle, which leads to update statistical characteristics of the nodes. Second, a substitute data structure is configured during the second phase of each cycle based on the updated statistical characteristics. Third, the reference data structure is updated in accordance with the substitute data structure.

Dynamically optimizing decision tree inferences

According to one embodiment, a method, computer system, and computer program product for training a cognitive model that involves one or more decision trees as base learners is provided. The present invention may include constructing, by a tree building algorithm, the one or more decision trees, wherein the constructing further comprises associating one or more training examples with one or more leaf nodes of the one or more decision trees and iteratively running a breadth-first search tree builder on one or more of the decision trees to perform one or more tree building operations; and training the cognitive model based on the one or more decision trees.

Training decision tree-based predictive models

A non-volatile memory includes physical blocks each including a respective plurality of cells, where each cell is capable of storing multiple bits of data. A controller maintains dynamically resizable pools of physical blocks, including at least a low-density pool in which cells are configured to store fewer bits and a high-density pool in which cells are configured to store more bits. The controller repeatedly dynamically resizes the low-density and the high-density pools based on write utilization of the non-volatile memory.

Storage pool resizing to meet memory endurance targets

The invention relates to a method of operating a memory device comprising memory cells for storing information on N voltage levels separated by N−1 threshold voltages, the method comprising: obtaining a plurality of threshold voltage shift (TVS) patterns, each comprising N−1 TVS reference values representing expected shifts of the threshold voltages of a set of memory cells having a specific physical condition; assigning a matching TVS pattern to the set of memory cells; storing differences between actual TVS values of the memory cells and corresponding TVS reference values of the matching TVS pattern as TVS residual values; upon a reading instruction for a specified memory cell, determining restored TVS values by combining the matching TVS pattern of the corresponding set of memory cells with corresponding TVS residual values; and reading the information from the specified cell using the restored TVS values.

Storage of threshold voltage shifts

A technique for writing data to pages in a QLC block of a QLC NAND flash memory device, where the device comprises a plurality of SLC pages organized in SLC blocks and a plurality of QLC pages organized in QLC blocks. The technique comprises storing received data in SLC pages, dividing equally a QLC block in a predefined number of sub-blocks according to a corresponding QLC page health status of the pages of the QLC block. Upon determining that SLC pages are to be copied from SLC pages to QLC pages, copying device-internal the respective SLC pages to the sub-blocks of the QLC block using device-internal cache registers, where the copying is based on an error-count aware scheme.

Write and retire pages in QLC NAND blocks

An approach of accelerating inferences based on decision trees based on accessing one or more decision trees, wherein each decision tree of the decision trees accessed comprises decision tree nodes, including nodes grouped into one or more supersets of nodes designed for joint execution. For each decision tree of the decision trees accessed, the nodes are executed to obtain an outcome for the one or more decision trees, respectively. For each superset of the one or more supersets of said each decision tree, the nodes of each superset are jointly executed by: loading attributes of the nodes of each superset in a respective cache line of the cache memory processing said attributes from the respective cache line until an inference result is returned based on the one or more outcomes.

Joint execution of decision tree nodes for accelerating inferences

A non-volatile memory includes physical blocks each including a respective plurality of cells, where each cell is capable of storing multiple bits of data. A controller maintains dynamically resizable pools of physical blocks, including at least a low-density pool in which cells are configured to store fewer bits and a high-density pool in which cells are configured to store more bits. The controller determines whe ther total utilization of physical blocks is less than a low-density pool utilization threshold above which the high-density pool of physical blocks is utilized for storing host write data and additionally identifies cold in-use logical block address (LBA) regions having low total access frequencies. Based on determining the total utilization of physical blocks is less than the low-density pool utilization threshold, the controller performs data placement of data from the cold in-use LBA regions in blocks of the high-density pool.

Proactive data placement in high density storage by a hybrid non-volatile storage controller

Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.

Calibration of threshold voltage shift values

A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.

Detecting and managing under-program failures in non-volatile memory

Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.

Accelerating decision tree inferences

A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Page group read voltage threshold calibration

A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

Latency in data storage systems

An embodiment for root cause analysis of computerized system anomalies is provided. The embodiment may include monitoring key performance indicators (KPIs) for a computerized system, wherein KPI values of the monitored KPIs form respective timeseries. The embodiment may include detecting an anomaly in the computerized system based on the monitored KPIs. The embodiment may include determining a troubleshooting time window extending over a given time period. The embodiment may include identifying a strict subset of the monitored KPIs based on portions of the respective timeseries spanning the given time period. The strict subset comprises abnormal KPIs (aKPIs) and potential explanatory KPIs (xKPIs). The embodiment may include obtaining a causal graph of vertices mapping KPIs of the strict subset by running a causality algorithm to evaluate weights of directed edges connecting the vertices and accordingly obtain one or more directed paths. The embodiment may include returning the obtained causal graph.

Root cause analysis of computerized system anomalies based on causal graphs

In an approach for constructing an ensemble model from a set of base learners, a processor performs a plurality of boosting iterations, where: at each boosting iteration of the plurality of boosting iterations, a base learner is selected at random from a set of base learners, according to a sampling probability distribution of the set of base learners, and trained according to a training dataset; and the sampling probability distribution is altered: (i) after selecting a first base learner at a first boosting iteration of the plurality of boosting iterations and (ii) prior to selecting a second base learner at a final boosting iteration of the plurality of boosting iterations. A processor constructs an ensemble model based on base learners selected and trained during the plurality of boosting iterations.

Constructing an ensemble model from randomly selected base learners

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Thalwil, Switzerland

Charalampos Pozidis