Abb Schweiz Ag

Hitachi Energy Ltd

Hitachi Energy Switzerland Ag

Abb Power Grids Switzerland Ag

Charalampos Papadopoulos

Munaf Rahimo

Chiara Corvasce

Arnost Kopta

Samuel Hartmann

Dominik Truessel

David Guillon

Sven Matthias

Fabian Fischer

Elizabeth Buitrago

A reverse conducting insulated gate power semiconductor device is provided which comprises a plurality of active unit cells () and a pilot diode unit cell () comprising a second conductivity type anode region () in direct contact with a first main electrode () and extending from a first main side () to a first depth (d). Each active unit cell () comprises a first conductivity type first source layer () in direct contact with the first main electrode (), a second conductivity type base layer () and a first gate electrode (), which is separated from the first source layer () and the second conductivity type base layer () by a first gate insulating layer () to form a first field effect transistor structure. A lateral size (w) of the anode region () in an orthogonal projection onto a vertical plane perpendicular to the first main side () is equal to or less than 1 μm. On a first lateral side surface of the anode region () a first insulating layer () is arranged and on an opposing second lateral side surface of the anode region () a second insulating layer () is arranged. And a distance between the first insulating layer () and the second insulating layer () is equal to or less than 1 μm, the first insulating layer () extending vertically from the first main side () to a second depth (d), and the second insulating layer () extending vertically from the first main side () to a third depth (d), wherein the first depth (d) is less than the second depth (d) and less than the third depth (d).

Reverse conducting insulated gate power semiconductor device having low conduction losses

The present application provides a power semiconductor module, including a support which carries at least one power semiconductor device, the support together with the power semiconductor device is at least partly located in a housing, the support and the power semiconductor device are at least partly covered by a sealing material, additionally to the sealing material, a protecting material is provided in the housing, the protecting material is formed from silicon gel and the protecting material at least partly covers at least one of the support, the power semiconductor device and the sealing material.

Power semiconductor module

A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 &#x3bc;m. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.

Power semiconductor device and method for manufacturing such a power semiconductor device

The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 &#x3bc;m from the second plane in a direction towards the wafer.

Power semiconductor device with thick top-metal-design and method for manufacturing such power semiconductor device

Growing community of inventors

Lenzburg, Switzerland

Charalampos Papadopoulos