Taiwan Semiconductor Manufacturing Comp. Ltd.

Chaos Tsai

Feng-Jia Shiu

Wen-Chen Lu

Hung-Wen Cho

A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension Wof the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension Walong the first direction and are about equally distanced from the main layout pattern by a dimension D. The dimensions Wand Dare greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.

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Hsin-Chu County, Taiwan

Chaos Tsai