Samsung Electronics Co., Ltd.

Huawei Technologies Co., Limited

Intel Corporation

Future Wei Technologies, Inc.

Chaohong Hu

Hongzhong Zheng

Dimin Niu

Uksong Kang

Liang Yin

Mu-Tien Chang

Frederic Sala

Kiran Pangal

Sandeep K Guliani

Balaji Srinivasan

Zhan Ping

Suhas

Chun Liu

Xin Liao

Krishna Teja Malladi

Zhou Yu

Bob Brennan

Jea Woong Hyun

Prashant Jayaprakash Nair

A method of operating a computing system comprises defining a zoned namespace for non-volatile memory (NVM) of a memory device of the computing system, the zoned namespace including multiple NVM zones of multiple non-overlapping logical block addresses (LBAs) of the NVM, mapping persistence logging (PLOG) identifiers (IDs) to the NVM zones, a PLOG ID identifying a PLOG zone of one or more NVM zones, and performing a PLOG-specific access operation on a PLOG zone of the NVM in response to a PLOG-specific command received from a host device of the computing system.

Persistence logging over NVM express for storage devices application

Write operation and garbage collection methods are provided for a Solid State Drive (SSD) controller of a SSD having Not-AND (NAND) flash memory devices with on-die Static Random Access Memory (SRAM) and NAND flash memory. In the write operation method, a received block of data is stored in on-die SRAM of the NAND flash device, rather than in on-chip SRAM of the controller, prior to programming into NAND flash memory. Until programmed into NAND flash memory, the block of data remains available in the on-die SRAM to fulfill an 'immediate read' operation, if received. In the garbage collection method, blocks of data are read from one or more source NAND flash devices and stored in on-die SRAM of a destination NAND flash device until a limit of such blocks has been reached, then the destination NAND flash device programs the blocks from the on-die SRAM into NAND flash memory.

Method for using NAND flash memory SRAM in solid state drive controller

A multi-instance 2-Level-Memory (2LM) architecture manages access by processing instances having different memory usage priorities to memory having different performance and cost levels. The 2LM architecture includes a virtual memory management module that manages access by respective processing instances by creating memory instances based on specified memory usage priority levels and specified virtual memory sizes and defining policies for each usage priority level of the created memory instances. In response to a virtual memory request by a processing instance, the virtual memory management module determines whether a virtual memory size at a designated usage priority level requested by a processing instance can be satisfied by a policy of a created first memory instance and, if not, selects another memory instance that can satisfy the requested virtual memory size at the designated usage priority level and swaps out the first memory instance in favor of the other memory instance.

Multi-instance 2LM architecture for SCM applications

A computing system including: a host interface configured to parse a command packet from a command address medium; and a command block, coupled to the host interface, configured to: assemble a command from the command packet.

Computing system with communication mechanism

An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

Memory system architectures using a separate system control path or channel for processing error information

A method implemented by a memory device, comprising obtaining, by a processor coupled to a memory, a wear-leveling policy from an application executable at the memory device, wherein the wear-leveling policy indicates a memory size by which to perform wear-leveling within an instance, wherein the instance comprises an address range assigned to the application in the memory of the memory device, obtaining, by a processor, a request to access the instance, and performing, by the processor, wear-leveling on a plurality of memory cells within the instance according to the wear-leveling policy.

Application defined multi-tiered wear-leveling for storage class memory systems

An embodiment includes a module, comprising: a memory bus interface; circuitry; and a controller coupled to the memory bus interface and the circuitry, and configured to: collect meta-data associated with the circuitry; and enable access to the meta-data in response to a memory access received through the memory bus interface.

Memory system architecture

A method of deduplicating memory in a memory module includes identifying a hash table array including hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying a plurality of virtual buckets each including some of the physical buckets, and each sharing at least one of the physical buckets with another of the virtual buckets, hashing a block of data according to a corresponding one of the hash functions to produce a hash value, determining whether an intended physical bucket has available space for the block of data according to the hash value, and determining whether a near-location physical bucket has available space for the block of data when the intended physical bucket does not have available space, the near-location physical bucket being in a same one of the virtual buckets as the intended physical bucket.

Virtual bucket multiple hash tables for efficient memory in-line deduplication application

A computing system includes: a host memory including a driver and an address map; a host central processing unit, coupled to the host memory, configured to divide a command to a command packet with the driver, map the command packet to the address map, and deliver the command packet based on the address map over a command address medium.

Computing system with communication mechanism and method of operation thereof

A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application

A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.

Memory devices and modules

A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.

A deduplication memory module, which is configured to internally perform memory deduplication, includes a hash table memory for storing multiple blocks of data in a hash table array including hash tables, each of the hash tables including physical buckets and a plurality of virtual buckets each including some of the physical buckets, each of the physical buckets including ways, an address lookup table memory (ALUTM) including a plurality of pointers indicating a location of each of the stored blocks of data in a corresponding one of the physical buckets, and a buffer memory for storing unique blocks of data not stored in the hash table memory when the hash table array is full, a processor, and memory, wherein the memory has stored thereon instructions that, when executed by the processor, cause the memory module to exchange data with an external system.

Growing community of inventors

San Jose, CA, United States of America

Chaohong Hu