Rambus Inc.

Tram, Inc.

Pulse Biosciences, Inc.

Samsung Display Co., Ltd.

T-ram Semiconductor, Inc.

Chaofeng Huang

Shahram Abdollahi-Alibeik

Amir Amirkhany

Gregory P Schaadt

Kenneth Robert Krieg

Brian S Leibowitz

Huy M Nguyen

John M Wilson

Lei Luo

Michael D Bucher

Hsuan-Jung (Bruce) Su

Kun-Yung Chang

Jared L Zerbe

Kevin S Donnelly

Thomas H Lee

Wayne S Richardson

Kambiz Kaviani

Wayne D Dettloff

Grace Tsang

Clemenz L Portmann

Hajee Mohammed Shuaeb Fazeel

Andy Chan

Gundlapalli Shanmukha Srinivas

Described herein are apparatuses and methods for applying high voltage, high current, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., while preventing damage from load arcing. Some of the apparatuses and methods described herein may limit the load and pulsed power source current in case of load arcing significantly by using a transmission line (e.g., coaxial cable, twisted pair or parallel pair cables) between the pulsed power source and the load having a length configured to achieve this goal.

Apparatuses and methods for limiting load current in nanosecond pulsed power sources

Described herein are apparatuses and methods for applying high voltage, sub-microsecond (e.g., nanosecond range) pulsed output to a biological material, e.g., tissues, cells, etc., using a high voltage (e.g., MOSFET) gate driver circuit having a high voltage isolation and a low inductance. In particular, described herein are multi-core pulse transformers comprising independent transformer cores arranged in parallel on opposite sides of a substrate. The transformer cores may have coaxial primary and secondary windings. Also describe are pulse generators including multi-core pulse transformers arranged in parallel (e.g., on opposite sides of a PCB) to reduce MOSFET driver gate inductance.

Nanosecond pulsed power sources having multi-core transformers

Described herein are apparatuses (e.g., systems and devices) and methods of delivering nanosecond pulsed electrical fields (nsPEF). In particular, these apparatuses and methods may provide enhanced safety and robust operation over even very short (e.g., nanosecond and sub-nanosecond pulses) and high voltage pulsing; these benefits may be accomplished by multi-functional isolation of various subsystems and components of the apparatus, even including the low-voltage, control and command portions of the apparatus with extremely low capacitance, high voltage isolation.

Nanosecond pulsed electric field system

A power converter including: a regulator including an output terminal to output an output voltage according to a first reference voltage, the output terminal to be coupled to a load; and a controller coupled to the output terminal, the controller to increase a current at the output terminal when a voltage at the output terminal is lower than a second reference voltage, and to decrease the current at the output terminal when the voltage at the output terminal is greater than a third reference voltage.

Power converter system and method of operating thereof

An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

On-chip regulator with variable load compensation

An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.

Multi-modal communication interface

High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such 'differential' or 'non-uniform' sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested &#x201c;DAC within a DAC&#x201d; arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

High resolution output driver

Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.

Methods and circuits for calibrating multi-modal termination schemes

An apparatus and method for producing dummy data is based on timing paths co-located with the address/data paths of the memory. An output clock generator uses the dummy data. The technique for producing dummy data is particularly important for memory systems in which the output of memory cells do not normally provide large voltage swings, making them less practical for self timing approaches to dummy data generation.

Apparatus and method for producing dummy data and output clock generator using same

An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the memory, and is responsive to an address emulation signal produced by the clock generator to provide dummy data near the output structures. An output clock signal with an adjustable phase and a dummy data reference clock signal on the input of the clock channel are generated. A phase detector near the output structures, determines whether the output clock is early, late or on time with respect to the dummy data. Logic signals are produced at the phase detector, and returned to the clock generator for adjusting the relative phase of the output clock signal.

Architecture and method for output clock generation on a high speed memory device

Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.

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San Jose, CA, United States of America

Chaofeng Huang