Intel Corporation

Chaodan Deng

Nasser A Kurd

Thomas P Thomas

Songmin Kim

Navindra Navaratnam

A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.

Adjusting PLL/analog supply to track CPU core supply through a voltage regulator

According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.

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Portland, OR, United States of America

Chaodan Deng