Taiwan Semiconductor Manufacturing Comp. Ltd.

Chaochieh Tsai

Shyh-Chyi Wong

Chung-Long Chang

Peter Yu Fei Huang

Shyhchyi Wong

Chao-Cheng Chen

Jui-Yu Chang

Ssu-Pin Ma

Heng-Ming Hsu

Liang-Kun Huang

Richard Burton Cassidy, Ii

Peter Yu-Fei Huang

Ju-Yu Chang

A three-dimensional stacking structure is described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die includes contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection.

Three-dimensional stacking structure

A package structure and method for forming the same are provided. The package structure includes a first die, and the first die includes a first magnetic pad formed over a first substrate. The package structure includes a second die, and the second die includes a second magnetic pad formed over a second substrate. The package structure also includes a hybrid bonding structure formed between the first die and the second die of the second wafer. The hybrid bonding structure includes a magnetic bonding structure which is made of the first magnetic pad and the second magnetic layer.

Package structure having magnetic bonding between substrates

A three-dimensional stacking structure and the manufacturing method(s) thereof are described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die include contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection.

Three-dimensional stacking structure and manufacturing method thereof

Described is a method where a seal ring is formed by stacking interconnected conductive layers along the perimeter of an integrated circuit (IC). The seal ring is formed continuously around the IC perimeter using a conductive chain with two distinct widths. Each section of distinct width forms a transmission having a distinct characteristic impedance. Unwanted signals may be coupled to the seal ring from signal bond pads or from internal circuitry. Because of the impedance mismatch between the different width sections of the seal ring transmission lines, only a portion of each signal is propagated through each seal ring discontinuity while the remainder is reflected. As the signal passes through multiple discontinuities in the seal ring, it is further attenuated, reducing propagation of unwanted signals. This is accomplished while preventing moisture intrusion into the IC.

RF seal ring structure

A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.

Self-aligned process for a stacked gate RF MOSFET device

A method and structure for a device with a signal line over a semiconductor structure where the signal line is formed over the ground plane, passivation layer, and polyimide layer. We provide a semiconductor structure comprising a substrate having devices formed thereover and a plurality of insulating and conductive layers thereover. Next, we form ground plane over the semiconductor structure. The ground plane is the top metal layer over an inter metal dielectric layer. We then form a passivation layer over the ground plane. We form a first dielectric (e.g., polyimide) layer over the passivation layer. Subsequently, we form a signal line over the first dielectric layer. The signal line is formed by a plating or printing. We form a second dielectric layer (e.g., polyimide over the signal line and the first dielectric layer.

Lossless microstrip line in CMOS process

A new method and structure is provided to connect a planar, spiral inductor to underlying interconnect metal, the interconnect metal has been created over a semiconductor surface. A layer of dielectric followed by a layer of passivation is deposited over the semiconductor surface, including the surface of the underlying interconnect metal. Large first vias are created through the layers of passivation and dielectric. The large first vias align with the patterned interconnect metal, providing low-resistivity points of interconnect between the spiral inductor, which is created on the surface of the layer of passivation concurrent with the creation of the large first vias, and the patterned interconnect metal. A thick layer of polyimide is deposited over the surface of the layer of passivation, including the surface of the spiral inductor and the large first vias. The invention can further be extended by creating at least one second via through the thick layer of polyimide aligned with at least one of the created first vias. A patterned and etched layer of metal that fills the second via creates a re-distribution layer on the surface of the thick layer of polyimide for flip chip interconnects.

Structure to reduce the degradation of the Q value of an inductor caused by via resistance

A method and structure for a device with a signal line over a semiconductor structure where the signal line is formed over the ground plane, passivation layer, and polyimide layer. We provide a semiconductor structure comprising a substrate having devices formed thereover and a plurality of insulating and conductive layers thereover. Next, we form ground plane over the semiconductor structure. The ground plane is the top metal layer over an inter metal dielectric layer. We then form a passivation layer over the ground plane. We form a first dielectric (e.g., polyimide) layer over the passivation layer. Subsequently, we form a signal line over the first dielectric layer. The signal line is formed by a plating or printing. We form a second dielectric layer (e.g., polyimide) over the signal line and the first dielectric layer.

A structure and method of manufacturing a CMOS device where the Coplanar wave guide (CPW) lines are formed above the top metal lines. Also other insulating layers are provided that reduce the e-field from the signal line to the substrate. There are four embodiments. In the first embodiment, the following layers are formed over the semiconductor structure: the passivation layer, a shielding layer, a first insulator layer, a high K dielectric layer, a CPW and a second insulator layer. In the second embodiment, no shielding layer is used and the high k dielectric layer is thicker than in the first embodiment. In the third embodiment, a thick shielding layer is used and no high k dielectric layer. In the fourth embodiment, the top metal layer is used as a shielding layer and no high k dielectric layer is used.

Lossless co-planar wave guide in CMOS process

A new method is provided for the creation of an inductive over the surface of a semiconductor substrate. A first layer of metal is created in a layer of dielectric, a second layer of metal is created overlying the first layer of metal. The first layer of metal combined with the second layer of metal form an inductor of increased height, reducing the resistivity of the inductor, increasing the Q value of the inductor. The new method of creating an inductor can be combined with creating contact points that connect to contact points in the active region of the surface of a semiconductor substrate.

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Hsin-Chu, Taiwan

Chaochieh Tsai