Stmicroelectronics Asia Pacific Pte Limited

Chaochao Zhang

Dianbo Guo

Chee Weng Cheong

Baranidharan Karuppusamy

Kien Beng Tan

Kusuma Adi Ningrat

Praveesh Chandran

Giuseppe Noviello

Leonard Liviu Dinu

EngJye Ng

Leonard Dinu

Nee Loong Wilson Low

Disclosed herein is a touch screen controller for controlling touch sensing in a touch screen display, the touch screen display having a display layer controlled as a function of horizontal sync and vertical sync signals and a capacitive touch array comprised of drive lines and sense lines. The touch screen controller includes a driver and control circuitry. The control circuitry is configured to cause the driver to generate a driving signal on the drive lines during assertion of the horizontal sync signal, and cause the driver to generate the driving signal on the drive lines during assertion of the vertical sync signal. Analog touch sensing circuitry is configured to generate analog touch data as a function of signals on the sense lines resulting from generation of the drive signal on the drive lines.

Reduction of noise in touch data samples via sampling during porch time of Vsync and Hsync signals

An active stylus is capacitively coupled to a capacitive touch panel for communication. The active stylus operates in a wait mode to receive initial communications from the panel. In response to such receipt, the active stylus synchronizes to a repeating communications frame implementing time division multiplexing. Communications from the active stylus to the panel include: information communications; synchronization communications and communications specific for columns and/or rows of the panel. Communications from the panel to the active stylus may be addressed uniquely to the stylus or commonly to a group of styluses.

System and method of communication between a capacitive touch screen and an active stylus

A charge sensing circuit generates a voltage in a sensing period that is indicative of sensed charge. The generated voltages are accumulated by an accumulator circuit over a number of sensing periods. A noise detection circuit senses when the voltage generated by the charge sensing circuit is outside of a boundary and generates a detection signal in response thereto. A control circuit, in response to the detection signal, controls the accumulator circuit to block accumulation of the voltages generated by the charge sensing circuit during at least the sensing period in which the detection signal is generated. An analog-to-digital converter circuit then converts an accumulated output voltage from the accumulator circuit to a digital value at the end of an accumulation time period that includes the sensing periods. The end of the accumulation time period is delayed by at least one sensing period in response to the detection signal.

Method and apparatus for blocking accumulation of electrical fast transient (EFT) noise

A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.

Chip synchronization by a master-slave circuit

A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.

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Singapore, Singapore

Chaochao Zhang