Micron Technology Incorporated

Globalfoundries Singapore Pte. Ltd.

Chao Zhu

David A Kewley

Adam L Olson

Xiaosong Zhang

Merri Lyn Carlson

Md Zakir Ullah

Tien Minh Quan Tran

Kok Siak Tang

Mohammad Moydul Islam

Zhigang Yang

Hui Chin Chong

Juan Boon Tan

Wanbing Yi

Shunqiang Gong

Wei Shao

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

Microelectronic devices with tiered decks of aligned pillars exhibiting bending and related methods

Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, 'pillar density' being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Microelectronic devices with tiered decks of differing pillar density and related methods and systems

Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include Mto Mmetal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level Mincludes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having M. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between Mand its adjacent underlying metal level M.

Semiconductor device and method of forming thereof

Growing community of inventors

Singapore, Singapore

Chao Zhu