Beijing Superstring Academy of Memory Technology

University of Science and Technology Beijing

The Procter Gamble Company

Tsinghua University

Chao Zhao

Jie Chen

Guilei Wang

Zhengyong Zhu

Bokmoon Kang

Jin Zhang

Cheng Zhang

Xiangsheng Wang

Jinfeng Huang

Mark Andrew Thornton

Xuezheng Ai

Wenhua Gui

Lu Ji

Kaitian Wang

Jayson Oxcena Gawaran

Minchen Du

Zhensheng Liu

Ankan Mandal

Xuejiao Sun

A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

Semiconductor device, manufacturing method therefor, and electronic equipment

A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data. During a reading operation, a second voltage is applied to the auxiliary electrode through the word line by using the influence of the voltage on the auxiliary electrode on the threshold voltage of the transistor (the size of the second voltage is between the threshold voltage of the transistor when storing '1' and the threshold voltage of the transistor when storing “0”), and then the data is read by detecting the size of the output current of the field effect transistor.

Semiconductor memory device, manufacturing method thereof and electronic device

A low-carbon and low alloy hot-work die steel with a high toughness at low temperatures and a high strength at high temperatures and a high hardenability, comprises the following components: C: 0.15-0.35%, Si: 0.40-0.90%, Mn: ≤0.80%, Cr: 1.50-2.40%, Ni: 2.50-4.50%, Mo: 1.00-1.60%, V: 0.10-0.40%, W: 0.20-0.90%, P: ≤0.02%, S≤0.02%, and a balance of Fe matrix and other inevitable impurities. The above percentages are mass percentages. The material of the present invention can have a V notch impact energy of 30 J or more than 30 J at −40° C., a high temperature strength of 380 MPa or more at 700° C., and a hardenability of 200 mm or more to ensure the consistency of internal and external microstructures. The materials of the present invention can be applied to hot-work molds used in special working conditions that require high toughness at low temperatures, high strength at high temperatures and high hardenability.

Hot-work die steel with high toughness at low temperatures and high strength at high temperatures and high hardenability and preparation method thereof

A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.

Memory and manufacturing method thereof, and electronic device

Growing community of inventors

Beijing, China

Chao Zhao