Chinese Academy of Sciences

University of Science and Technology Beijing

Other

The Procter Gamble Company

Interuniversitair Micorelektronica Centrum (Imec, Vzw)

Pixel Biotech (Shanghai) Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec

Chao Zhao

Huicai Zhong

Junfeng Li

Qingqing Liang

Jun Luo

Huilong Zhu

Dapeng Chen

Chunlong Li

Tao Yang

Jiang Yan

Wenwu Wang

Guilei Wang

Cheng Zhang

Qiuxia Xu

Jinbiao Liu

Xiaobin He

Jinjuan Xiang

Jin Zhang

Huaxiang Yin

Xinyu Liu

Ke Wei Wei

Junjie Li

Gaobo Xu

Jian Deng

Jianqiang Li

Xinhua Wang

Sen Huang

Da Ye Yang

Jinfeng Huang

Yong Lian

Jie Chen

Jianfeng Gao

Eduard Albert Cartier

Hong Yang

Shi Xia Liu

Tianchun Ye

Kai Han

Xiaolei Wang

Huajie Zhou

Qiang Xu

Zuozhen Fu

Lingkuan Meng

Lijun Dong

Honggang Liu

Mark Andrew Thornton

Yajuan Su

Lu Ji

Kunpeng Jia

Wen Ou

Zhensheng Liu

Xuejiao Sun

Kaitian Wang

Jayson Oxcena Gawaran

Minchen Du

Ankan Mandal

Hushan Cui

Chengjun Huang

Qilong Bao

Yuqiang Ding

Guanglu Chen

Yihong Lu

Junfong Li

Jerry Chen

A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

MRAM, method of manufacturing the same, and electronic device including the MRAM

The present application provides a low carbon martensitic high temperature strength steel and a preparation method thereof, wherein the chemical composition of the low carbon martensitic high temperature strength steel are: C: 0.10-0.25 wt %, Cr: 10.0-13.0 wt %, Ni: 2.0-3.2 wt %, Mo: 1.50-2.50 wt %, Si&#x2264;0.60 wt %, Mn&#x2264;0.60 wt %, W: 0.4-0.8 wt %, V: 0.1-0.5 wt %, Co: 0.3-0.6 wt %, Al: 0.3-1.0 wt %, Nb: 0.01-0.2 wt %, and a balance of Fe. The high temperature strength steel of the present application achieves high strength at high temperature by simultaneously precipitating both nano-coherent carbides and intermetallic compounds. It has an excellent toughness, and can be used for certain structural parts under special working conditions, such as aero-engines to increase its service life and service temperature.

Low carbon martensitic high temperature strength steel and preparation method thereof

The present application provides a hot-work die steel and a preparation method thereof wherein the chemical constituents of the hot-work die steel in mass percentage are as follows: C: 0.20-0.32 wt %, Si: &#x2264;0.5 wt %, Mn: &#x2264;0.5 wt %, Cr: 1.5-2.8 wt %, Mo: 1.5-2.5 wt %, W: 0.5-1.2 wt %, Ni: 0.5-1.6 wt %, V: 0.15-0.7 wt %, Nb: 0.01-0.1 wt %, and a balance of iron, wherein an alloying degree is 5-7%; a tensile strength of the hot-work die steel at 700&#xb0; C. is 560-700 MPa; a value of hardness of the hot-work die steel at room temperature is 32-38 HRC after holding at 700&#xb0; C. for 3-5 h; and the hot-work die steel has an elongation of 14% to 16% at room temperature, a percentage reduction of area of 48% to 65%, and an impact toughness of 52-63 J at room temperature. The hot-work die steel of the present application has an excellent thermal stability as well as a good plasticity and a toughness at room temperature.

Hot-work die steel and a preparation method thereof

A dual-chamber package system for absorbent articles, comprises: a retaining chamber configured to vertically retain a plurality of absorbent articles, a dispensing chamber positioned underneath the retaining chamber, wherein the dispensing chamber has a front side opening, and a divider separating the retaining chamber and the dispensing chamber, wherein at least a portion of the divider is moveable so that a bottommost absorbent article is configured to be dispensed from the front side opening of the dispensing chamber.

Dual-chamber package system for absorbent articles

The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.

Transistor having a gate with a variable work function and method for manufacturing the same

A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

Low interface state device and method for manufacturing the same

A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2, m&#x2265;1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

Method of monolithic integration of hyperspectral image sensor

A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.

Method and arrangement for reducing contact resistance of two-dimensional crystal material

A particle screening device is provided. The particle screening device comprises: a substrate including a first side and a second side opposite to the first side; a micropore array formed on the substrate, wherein each micropore penetrates through the substrate from the first side to the second side and has a size configured to at least permit particles smaller than target particles flow through; and electrodes formed on at least one side of the first and second sides of the substrate and around at least some micropores, wherein the electrodes are configured to generate an electric field at corresponding micropores.

Particle screening device

A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.

Method for manufacturing semiconductor device

A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.

Planarization process

A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.

GaN-based power electronic device and method for manufacturing the same

A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a titanium precursor are introduced into the reaction chamber, wherein the aluminum precursor has a molecular structure of a structural formula (I); and the aluminum precursor and the titanium precursor are brought into contact with the substrate so that a titanium-aluminum alloy thin film is formed on the surface of the substrate by vapor deposition. The method solves the problem of poor step coverage ability and the problem of incomplete filling with regard to the small-size devices by the conventional methods. Meanwhile, the formation of titanium-aluminum alloy thin films with the aid of plasma is avoided so that the substrate is not damaged by plasma.

Method for preparing titanium-aluminum alloy thin film

There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.

Methods for manufacturing semiconductor devices

Growing community of inventors

Kessel-lo, Belgium

Chao Zhao