Emc Corporation

Intel Ndtm US LLC

Chao Zhang

Robert Tower Frey

Krishna Kumar Parat

Richard M Fastow

Xin Sun

Poulo Kuriakose

Rajesh Ananthanarayanan

Hawkins Yao

Ricardo Basco

Heonwook Kim

Zhan Liu

Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

Weak erase pulse

Systems and methods in accordance with various embodiments relate to a storage switch including task processing synchronization. In embodiments of the present invention, the packet processing units may generate and store Task Index and Generation Count information that prevents the processing of expired commands or responses. Additionally or alternatively, embodiments of the present invention may further employ timeout sequences to prevent previous instances of a stale task resource from disrupting the current use of the task resource.

Storage switch task processing synchronization

A storage switch is disclosed that facilitates mirroring of data. For example, a target is mirrored when an identical (or almost identical) copy of the data is stored in two or more separate physical data stores. Because the various data stores may not be homogenous, they may provide for different burst sizes. To accommodate the different burst sizes, the switch provides different sequence counts for data packets sent to the different data stores that store the mirrored data.

Storage switch mirrored write sequence count management

A switch including a processor and method for monitoring bandwidth in the storage switch. The switch includes at least one physical port coupling at least one target and at least one initiator via the physical port. The monitoring method may include the steps of determining whether congestion occurs on the physical port and assigning a weight to bandwidth usage between the initiator and the target based on a minimum and maximum bandwidth settings for each target. The switch may further include a step of controlling bandwidth usage by each of said at least two targets based on minimum and maximum bandwidth settings for each of the targets.

Storage switch traffic bandwidth control

Systems and methods can provide mirrored virtual targets and online synchronization and verification of the targets while avoiding deadlock, inconsistencies between members of the target, and false verification failures. A lock within the storage switch can limit the number of outstanding commands for a physical target to one during synchronization and verification operations. In one embodiment, a lock can be implemented as one or more resource tables maintaining an indication of the number of transfer ready signals available from physical targets. During typical write operations, deadlock can be avoided by determining whether each physical target for the mirrored operation can issue a transfer ready signal prior to issuing a command to the physical target. When a synchronization or verification operation begins, the maximum available number of transfer ready signals for each target can be decremented to one in order to limit the total number of outstanding commands for each target to one.

Systems and methods to avoid deadlock and guarantee mirror consistency during online mirror synchronization and verification

Systems and methods in accordance with various disclosed embodiments can manage a mirrored virtual target to synchronize the members of the virtual target and/or to verify that the members of the virtual target are synchronized. In one embodiment, a mirrored virtual target is synchronized by first provisioning at least one first internal virtual logical unit (IVLU) corresponding to at least one destination target of the mirrored target and a second IVLU corresponding to a source target of the mirrored target. A write command is first issued, via one or more internal virtual logical units, to each of the destination target members of the mirrored target. When each destination target is available to receive data, as evidenced by a returned transfer ready signal, a read command is provided to the source target via the second internal virtual logical unit. In this manner, a data path between the source and destination targets is established prior to reading data from the source target. Accordingly, the data can be read from the source target, converted to write data, and routed to the destination targets at line speed without buffering of the data. A similar process is provided to verify that the members of a mirrored target are synchronized. In one embodiment, a system and method is provided to manage incoming commands for the mirrored target while synchronizing or verifying synchronization of the mirrored target. Incoming commands can be queued as they are received and provided to the mirrored target when pending synchronization or verification commands are completed.

Online initial mirror synchronization and mirror synchronization verification in storage area networks

Systems and methods in accordance with various embodiments can detect and alleviate potential or actual deadlock of a storage switch or storage area network when attempting to write data to a mirrored virtual target. In accordance with one embodiment, a timer is started when a storage switch routes a write command to the physical targets corresponding to a virtual target of the write command. If each physical target does not return a transfer ready resource within a predetermined timeout period, the switch determines that a potential or actual deadlock has occurred. An abort command is sent to each of the physical devices. The abort command can clear the command from the targets and also free any allocated transfer ready resources. After receiving an acceptance response from each physical target, the state of the write command at the switch can be cleared. The write command can then be re-issued to the physical devices. In one embodiment, a queue depth for the virtual target can be lowered after failing to receive transfer ready resources from each target. By decreasing the queue depth, the maximum number of commands the switch will process for a virtual target is decreased to decrease the probability of future deadlock. In one embodiment, the queue depth is increased after no deadlock is detected for a period of time.

Reactive deadlock management in storage area networks

One or more derived timers based on a source timer are provided to accommodate a plurality of periodic tasks while maintaining the high resolution of the source timer. To accommodate a number of periodic tasks, a number of derived timers can be selected utilizing a novel method based on the number of periodic tasks that are most time-critical, the number of tasks that are less time-critical, and the number of tasks that can be performed during the source timer interval. The interval and start time for each derived timer is selected based the source timer and number of the derived timer. After establishing the derived timers, the most time-critical tasks can be assigned to the source timer and the less time-critical tasks arranged amongst the derived timers.

Growing community of inventors

Milpitas, CA, United States of America

Chao Zhang