Avatar Integrated Systems, Inc.

Siemens Industry Software Gmbh

Chao-Yung Wang

Ping-San Tzeng

Geng Bai

Yang Wu

Wen Kung Chu

Zhong Chen

A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin. A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.

Glitch power analysis and optimization engine

A signoff process includes: accessing circuit information of a circuit; performing, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern; performing, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the input pattern used in the power analysis and optimization; and outputting a simulation result to the analysis and optimization engine; wherein the analysis and optimization engine and the simulator are integrated.

Integrated simulator and analysis and optimization engine

A set of multi-corner multimode (MCMM) databases that correspond to a set of working scenarios are accessed. A full timing update on the set of MCMM databases, for the set of working scenarios, is applied. A graph based analysis (GBA) timing calibration is performed on the databases, for the set of working scenarios to obtain a set of GBA-calibrated databases. Multiphase optimizations on the set of GBA-calibrated databases are iteratively performed to generate a set of optimized databases, including: performing a phase-specific optimization on the set of GBA-calibrated database to obtain an improved set of databases, and recalibrating GBA timing on the set of improved databases prior to a next phase-specific optimization.

Graph-based timing analysis timing calibration

A graph-based analysis (GBA) output is obtained comprising timing information pertaining to a plurality of paths in an integrated circuit. A path-based analysis (PBA) is performed on the GBA output to analyze timing of the plurality of paths and generate a set of improved timing results; wherein the physical measurements used by the PBA are more accurate than the physical measurements used by the GBA. The PBA result is output to an optimizer to automatically adjust the circuit.

Circuit place and route optimization based on path-based timing analysis

A database is constructed based on a batch PBA performed on a plurality of paths of an integrated circuit. A local PBA is performed on a portion of a selected path. A selected optimization move is identified on the portion of the selected path, based on a result of the local PBA that best meets a set of constraints. A path-wide PBA is performed for an updated path that is based on the selected path incorporating the selected optimization move. The selected optimization move is committed in a netlist associated with the integrated circuit.

Local path-based analysis for circuit place and route optimization

A plurality of multi-corner multimode (MCMM) databases are accessed, wherein at least one of the plurality of MCMM databases corresponds to a first optimization scenario, and at least one of the plurality of MCMM databases corresponds to a second optimization scenario. A first optimization move is performed on paths in the first optimization scenario. The first optimization move is verified using GBA on paths in the second optimization scenario to determine that the first optimization move does not cause timing violations outside an MCMM database associated with the first optimization scenario.

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Taipei, Taiwan

Chao-Yung Wang