Huawei International Pte. Ltd.

National University of Singapore

Chao Yuan

Rui Yu

Theng Tee Yeo

Xuesong Chen

Yong Ping Xu

Kian Ann Ng

Liu Supeng

Supeng Liu

A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.

Time-to-digital converter

A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.

Digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit

Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.

Symmetrical capacitor arrays succesive approximation register (SAR) analog-to-digital converter (ADC)

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Singapore, Singapore

Chao Yuan