United Microelectronics Corp.

Ipenval Consultant Inc.

Silicon Integrated Systems Corporation

Chao-Yuan Huang

Ming-Sheng Yang

Hwi-Huang Chen

Yueh-Feng Ho

Juan-Yuan Wu

Water Lur

Peng-Yih Peng

An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.

Integrated circuit layout

A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.

Semiconductor device

A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Stacked chip system

A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 &#x3bc;m and a depth of at least 5 &#x3bc;m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.

Method for fabricating a through-silicon via

A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the metal layer react with the silicon in the gate and the source/drain to form a salicide. Then, any unreacted metal and the spacer are removed. An ion containing silicon is introduced into the source/drain. Finally, a second thermal treatment is performed.

Method of forming salicide

A method of fabricating a shallow trench isolation in semiconductor substrate comprises a densification process after performing chemical-mechanical polishing on an isolation plug. Thus, the isolation plug can prevent micro-scratches from forming deep scratches. Therefore, shorts arising from the micro-scratches do not happen.

Method of fabricating a shallow trench isolation

A method of fabricating a dual damascene is provided. A dielectric layer is formed on a substrate. A diffusion barrier layer is formed on the dielectric layer. A portion of the diffusion barrier layer and the dielectric layer is removed to form a trench and a via hole. A barrier layer is formed on the diffusion barrier layer and in the trench and the via hole. The barrier layer on the diffusion barrier layer is removed by chemical-mechanical polishing. A conductive layer is formed in the trench and the via hole by selective deposition. A planarization step is performed with the diffusion barrier layer serving as a stop layer.

Method of fabricating dual damascene structure

A photo-mask and a method of fabricating the same. A photo-mask comprises a quartz glass substrate, on which a clear area, a grey area, and a dark area formed over the quartz glass substrate. Incident light penetrates through the clear area completely, but only part of the incident light will go through the grey area since the other part of the incident light is absorbed by the grey area, On the other hand, incident light is blocked by the dark area completely.

Photo-mask and method of fabricating the same

A method of fabricating a via and an interconnection. On a substrate comprising a semiconductor device and a first metal layer, a first inter-metal dielectric layer is formed on the first metal layer. A photo-resist layer is formed on the first inter-metal dielectric layer. A single step of photolithography is performed to define a via hole region, an interconnection window region, and an isolation region simultaneously. The first inter-metal dielectric layer is etched using the photo-resist layer as a mask, to form a via hole and an interconnection window simultaneously. The photo-resist layer is removed and the via hole and the interconnection window are filled with a second metal layer. The second metal layer is etched until the inter-metal dielectric layer under the isolation region is exposed. A second inter-metal dielectric layer is formed.

Method of fabricating via and interconnection

A slurry filtration system for supplying a slurry to a polisher to perform a chemical mechanical polishing process. The system comprises a first three-way valve, to receive the slurry supplied from an external system; a slurry pump, to control the slurry flowing from the first three-way valve, and to maintain a circulating state of the slurry within the circulating system after the chemical mechanical polishing process comes to a stop; a slurry filter, to filter a plurality of large size particles in the slurry pumped from the slurry pump; a second three-way valve, to supply the slurry flowing from the filter to the polisher; and a transportation pipe, connecting between the first and the second three-way valves to transport the slurry from the second three-way valve back to the first three-way valve when the polishing process has stopped.

Growing community of inventors

Hsinchu, Taiwan

Chao-Yuan Huang