Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Yi Wang

Hon-Lin Huang

Chien-Hung Kuo

Ching-Hui Chen

Chen-Shien Chen

Mirng-Ji Lii

Chin-Yu Ku

Sheng-Yu Wu

Kai-Di Wu

Chun-Mao Chiu

Zi-Zhong Wang

Cheng-Lung Yang

Ming-Da Cheng

Wen-Hsiung Lu

Yu-Feng Chen

Kuo-Ching Hsu

Hong-Seng Shue

Cheng Jen Lin

Ming-Hong Cha

Chih-Hsiang Tseng

A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

Semiconductor device

A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

Semiconductor device and bump formation process

Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

Semiconductor devices

A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Semiconductor device and method of forming same

Semiconductor device and method of forming the same

A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.

A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.

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Tainan, Taiwan

Chao-Yi Wang