United Microelectronics Corp.

Chao-Yao Chiang

Kuo-Hsun Huang

Chien-Hung Zordius Chen

Chung-Chih Chang

Hsi-Chang Chang

The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate a first verified data. The processor performs a layout versus layout verification on the first verified data by using a user-defined verification tool of optical proximity correction data in a database to generate second verified data according to the reference layout data. The processor performs a second stage Boolean operation on the second verified data to generate a third verified data if the layout versus layout verification is successfully performed. The processor performs a Boolean check on the third verified data to generate fourth verified data using the reference layout data.

Optical proximity correction verification system and verification method thereof

A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool.

Planar design to non-planar design conversion method

A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value.

Computer implemented method for performing extraction

The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate first verified data. The processor performs a layout versus layout verification on the first verified data to generate second verified data by using the reference layout data. If the layout versus layout verification is successfully performed, the processor performs a second stage Boolean operation on the second verified data to generate third verified data. By using the reference layout data, the processor performs a Boolean check on the third verified data to generate fourth verified data.

A verifying method of an optical proximity correction is provided. The verifying method includes the following steps. A first netlist file is extracted from an integrated pre-OPC layout. A first post-OPC layout and a second post-OPC layout are merged to be an integrated post-OPC layout. A second netlist file is extracted from the integrated post-OPC layout. The first netlist file and the second netlist are compared.

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Hsinchu, Taiwan

Chao-Yao Chiang