Shenzhen China Star Optoelectronics Technology Co., Ltd.

Shenzhen Microbt Electronics Technology Co., Ltd.

Wuhan China Star Optoelectronics Technology Co., Ltd.

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Zte Corporation

Foxconn Technology Co., Ltd.

Fu Zhun Precision Industry (shen Zhen) Co., Ltd.

Gree Electric Appliances, Inc. of Zhuhai

Aac Acoustic Technologies (shenzhen) Co., Ltd.

American Audio Components Inc.

Tsinghua Shenzhen International Graduate School

Dong Guan Tai Hong Packaging Co., Ltd

Chao Xu

Zhijun Fan

Zuoxing Yang

Ke Xue

Nan Li

Haifeng Guo

Mo Chen

Tao Yang

Wei Wei

Xiong Zhang

Zhong Yu

Jianbo Liu

Zhou Zhi

Ming Xie

Xing-zhi Huang

Long Xie

De-Yu Wang

Jiang-Jun Hu

Ke Feng

Lianhua Duan

Wenxiu Wang

Xueyu Mei

Yuan Ma

Ruimin Li

Qilu Ye

Zhekang Luo

Yadong Zheng

Rong-Lin Ling-Hu

Shicai Long

Feng Feng

Pingfa Feng

Haijiang Lan

Deran Lyu

Changkuo Chen

Bin Ren

Longfei Shao

A test circuit (), including: a test sequence providing module (), configured to provide a test sequence (PRBS) to a to-be-tested sequential device (); a clock driving module (), configured to provide a clock signal () to the to-be-tested sequential device (), which includes a first clock driving circuit (), wherein the first clock driving circuit () includes: a plurality of first clock paths () which respectively provide corresponding clock signals (); and a logic unit () which generates, based on at least part of the clock signals () provided by the plurality of first clock paths (), a first clock signal with an adjusted pulse width, for the to-be-tested sequential device (); and a verification module (), configured to verify an output of the to-be-tested sequential device ().

Test circuit, test method, and computing system comprising test circuit for testing sequential circuit in pipeline stage

A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.

Computing device and computing system

The present disclosure relates to clock circuits, computing chips, hash boards and data processing devices. A clock circuit comprises M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein N inverters connected in series are arranged between an input port and an output port of each stage of the M stages of clock drive circuits, N being an odd number that is no less than 3. The clock circuit may provide clock signals with excellent performance.

Clock circuits, computing chips, hash boards and data processing devices

This disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard and a computing device. A pipeline clock driving circuit provides a pulse clock signal to a pipeline comprising multiple operation stages. The pipeline clock driving circuit includes multiple stages of clock driving circuits, each configured to provide the pulse clock signal to one corresponding operation stage; and a clock source coupled to an input of a first stage of clock driving circuit and configured to provide a basic clock signal. Inputs of other stages of clock driving circuits are coupled to outputs of previous stages of clock driving circuits. Each stage of clock driving circuit includes: a trigger; a delay module for outputting a delayed pulse signal to a next stage of clock driving circuit; and a combinational logic module for performing a combinational logic operation on the outputs to generate the pulse clock signal.

Pipeline clock driving circuit, computing chip, hashboard and computing device

A high-strength packaging bag with effects of heat preservation and watertightness is made of a composite paper. The composite paper includes an outer waterproof layer, an outer paper layer, a first adhesive layer, a heat-insulation and cushioning layer, a second adhesive layer, an inner paper layer and an inner waterproof layer arranged in sequence; and the first adhesive layer and the second adhesive layer are both elastic adhesive layers.

High-strength packaging bag with effects of heat preservation and watertightness, and preparation process thereof

The present disclosure provides a loudspeaker assembly and an electronic device, relating to the technical field of electronic devices, so as to solve the problems of single sound effect and lack of good sound effect. The loudspeaker assembly includes a first housing, a second housing, a loudspeaker vibrator and an adjusting mechanism. The first housing and the loudspeaker vibrator form a first cavity, and the second housing and the loudspeaker vibrator form a second cavity. The adjusting mechanism includes a driving mechanism and a filling part. The driving mechanism drives the filling part to move, so as to change the volume of the filling part extending into the second cavity.

Loudspeaker assembly and electronic device

Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Circuits and methods for performing hash algorithm

The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i&#x2212;1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Circuit for performing hash algorithm, computing chip, data processing device and method

This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

Computing chip, hashrate board and data processing apparatus

This disclosure relates to a device performing hash algorithm. A hash engine includes an operation module performing a hash operation on a data block and a clock module. The operation module includes operation stages each including registers and a combinational logic module. A digital signal based on the data block is sequentially delivered along the operation stages. Outputs of a first set of registers are coupled to an input of the combinational logic module of the current operation stage. Inputs of a second set of registers are coupled to an output of a combinational logic module of a previous operation stage. A clock signal, provided by the clock module to each operation stage, is sequentially delivered along a multi-stage clock driving circuits of the clock module. For the first and second sets of registers, a delivery direction of the digital signal is the same as that of the clock signal.

Clock tree, hash engine, computing chip, hash board and data processing device

A method for monitoring chatter in a machining process includes the following steps: collecting an original signal related to chatter in the machining process; for the original signal, obtaining a signal segment for calculation and analysis by updating data points in a sliding window with a set step-length, where the step-length refers to a number of data points updated every time in the sliding window, and is not greater than the size of the sliding window; calculating fractal dimensions of the signal segments in the sliding window by using a fractal algorithm; and comparing the calculated fractal dimension with an identification threshold to determine whether chatter occurs in the machining process. The measured signal does not need to be preprocessed by using the method, which can greatly improve calculation efficiency and can ensure accuracy of chatter identification.

Method for monitoring chatter in machining process

The present disclosure provides an OLED display device and a method of making the same. The method includes defining a recess in a first substrate; forming an alignment mark outside the recess; forming a second substrate in the recess; forming a thin film transistor layer and a pixel array layer sequentially on the second substrate. In the present disclosure, the first substrate is accurately aligned with mask plates when forming the pixel array layer, and the second substrate is not deformed during the process of vapor deposition, thereby avoiding the problem of color mixed in vapor deposition.

Method of making OLED display device having first substrate aligning accurately with mask plates

A method for manufacturing an organic electroluminescent display device is provided, which includes the steps of: providing a lower support substrate and an upper support substrate; making a lower flexible substrate and an organic electroluminescent device layer on the lower support substrate sequentially, making an upper flexible substrate and an adhesive layer on the upper support substrate sequentially; aligning the lower support substrate and the upper support substrate, to thereby attach the adhesive layer and the organic electroluminescent device layer; and peeling the lower support substrate and the upper support substrate. An organic electroluminescent display device made by the above manufacturing method is also provided. Accordingly, it can effectively solve the separating problem of a rigid substrate (a support substrate) and a flexible substrate, and the organic electroluminescent device is packaged directly in the manufacturing process, without additional thin film packaging device, therefore the manufacturing cost is greatly reduced.

Method of fabricating an organic electroluminescent display device

The present disclosure provides a double-sided display device which includes a first OLED display panel and a second OLED display panel, of which display surfaces are disposed facing away from each other, wherein the first and second OLED display panels have a common shared cathode layer; the first OLED display panel includes a first electron transport layer, a first emissive layer, a first hole transport layer, a first anode layer and a first array substrate that are sequentially laminated on a first surface of the shared cathode layer; and the second OLED display panel includes a second electron transport layer, a second emissive layer, a second hole transport layer, a second anode layer and a second array substrate that are sequentially laminated on a second surface of the shared cathode layer. The present disclosure further provides a manufacturing method of the double-sided display device as mentioned above. In comparison with the prior art, the present disclosure obtains a lighter and thinner double-sided display device.

Double-sided display device, manufacturing method thereof, and electronic apparatus

The present disclosure provides an organic light-emitting device and an organic light-emitting display apparatus. The organic light-emitting device includes a first electrode layer; an organic light-emitting layer disposed on a surface of the first electrode layer, wherein the organic light-emitting layer includes a light-emitting area and a non-light-emitting area; and a second electrode layer disposed on a surface of the organic light-emitting layer away from the first electrode layer, wherein the second electrode layer is correspondingly disposed on a surface of the non-light-emitting area such that light emitted from the light-emitting area passes through the second electrode layer.

Organic light-emitting device and organic light-emitting display apparatus

Growing community of inventors

Guangdong, China

Chao Xu