Mie Fujitsu Semiconductor Limited

Mosaic Systems, Inc.

Other

Suvolta, Inc.

Chao-Wu Chen

David Anthony Kidd

Vineet Agrawal

Lawrence T Clark

Richard Stephen Roy

Edward John Boling

Sang-Soo Lee

Samuel Leshner

Augustine Kuo

Ali Massoumi

Wasim Khaled

An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Slew based process and bias monitors and related methods

An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Integrated circuit process and bias monitors and related methods

A semiconductor circuit can include an array of static random access memory (SRAM) cells. A first SRAM cell may provide a first current through an insulated gate field effect transistor (IGFET) having a first conductivity type. A second SRAM cell may provide a second current through an IGFET having a second conductivity type. A first current division slew circuit can provide a first slew output current proportional to the first current to change the charge on a first slew capacitor. A second current division slew circuit can provide a second slew output current proportional to the second current to change the charge on a second slew capacitor. A pulse may be generated having a first edge determined by a launch signal and a second edge determined by the time the first or the second capacitor reach a predetermined potential.

SRAM performance monitor

A memory device that has an internal memory array provides timing signals to control the output timing of one or more redundant memory blocks that substitute for defective memory blocks in the internal memory array. In one embodiment, the internal memory array includes a pipelined output stage, and the timing signals ensure that the data is output from the memory devices in the order memory access requests are issued, even when the latency of the redundant memory blocks is less than the latency of the main memory array by up to two clock periods. In one embodiment, a FIFO memory queues the output data of the redundant memory blocks waiting to be output.

System and method for providing a redundant memory array in a semiconductor memory integrated circuit

A method is disclosed to carry out a data access operation in a data memory device that is subdivided into a plurality of memory arrays each array includes a plurality of memory cells accessible by an identifiable address. The method includes a step of asynchronously propagating in parallel a plurality of data access signals, each through a data access path over multiple propagation stages of signal lines interconnected between the memory arrays and each of the multiple propagation stages implementing an asynchronous local clock for receiving and sending said data access signals for carrying out said data access operation. The method further includes a step of adding a path delay in a selected set of the propagation stages to minimize a length of time difference in carrying out the data access operations through each of the different data access paths. The method further includes a step of generating a pulse train in each of the propagation stages for inputting to the local clock of a subsequent propagation stage for initiating the local clock of the subsequent propagation stage for propagating the data access signals.

Parallel asynchronous propagation pipeline structure to access multiple memory arrays

A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.

Growing community of inventors

San Jose, CA, United States of America

Chao-Wu Chen