Fujian Jinhua Integrated Circuit Co., Ltd.

Powerchip Technology Corporation

Chao-Wei Lin

Huixian Lai

Chia-Yi Chu

Yu Cheng Tung

Chiayi Chu

Yu-Cheng Tung

Chih-Yuan Chen

Janbo Zhang

Tsung-Wen Chen

Hui-Huang Chen

Ken-Li Chen

A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Shallow trench isolation structure and semiconductor device with the same

A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.

Semiconductor memory device

The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.

Memory device and manufacturing method thereof

A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

A novel method for manufacturing a 3-D vertical memory comprising the steps of dividing a multilayer structure composed of insulating intermediate layers and sacrificial intermediate layers into a first multilayer structure and a second multilayer structure, replacing the sacrificial intermediate layers in the multilayer structures with metal intermediate layers, and manufacturing the channel structure in two multilayer structures.

Growing community of inventors

Hsinchu County, Taiwan

Chao-Wei Lin