Realtek Semiconductor Inc.

Au Optronics Corporation

Chao-Wei Huang

Yen-Ju Lu

Yi-Hsin Lin

Ya-Ling Hsu

Sheng-Ju Ho

Chia-Hsuan Pai

Wang-Shuo Kao

Wen-Fang Sung

Chen-Tung Lin

Ching-Yeh Yu

Chen-Hsing Wang

Yuan-Nan Chiu

Wen-Tsan Chiou

A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.

Data processing apparatus and data accessing circuit

A display panel includes a first substrate, pixel structures, a second substrate, a display medium, a first sealant, and a second sealant. The first substrate includes an active area and a peripheral area outside the active area. The pixel structures are disposed on the active area of the first substrate. The second substrate is disposed opposite to the first substrate. The first sealant is disposed between the first substrate and the second substrate, and is located on the peripheral area of the first substrate. The second sealant is disposed on a side wall of the first substrate and a side wall of the second substrate. The second sealant includes a convex surface overlapped with the side wall of the first substrate and the side wall of the second substrate.

Display panel

The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.

Memory data access apparatus and method thereof

A display device includes a display panel, first and second conductive pads, a conductive adhesive layer and a circuit board. First and second leads are on a first substrate of the display panel and extended to be exposed at a side. A patterned electrode layer is on a second substrate of the display panel and partially exposed at the side. A spacer layer is on the first substrate and covers the first and second leads. A thickness of the spacer layer on the first lead is smaller than a thickness of the remaining part of the spacer layer. The first and second conductive pads are at the side of the display panel. The first conductive pads are extended to a space between the patterned electrode layer and the spacer layer on the first leads. The second conductive pads are connected to the second leads and the spacer layer thereon.

Display device

A processor circuit is provided. The processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a load instruction to generate a decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instruction is in a load-use scenario. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the load instruction according to the decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instruction is in the load-use scenario, the data buffer is configured to store the first address generated from the address generator, and store data requested by the load instruction according to the first address.

Processor circuit and data processing method

The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Ntime and read the specific data from the data cache memory for the Mtime, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Ntime; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.

Device and method for assisting processor in reading data

A transparent stereo display includes a first substrate, a second substrate, a common electrode, a display medium, and a patterned phase retardation film. A plurality of pixel structures is disposed on the first substrate. The pixel structures include a plurality of right eye pixel structures and left eye pixel structures. Each pixel structure includes a display region, a first region, and a second region. The patterned phase retardation film includes right eye polarized patterns and left eye polarized patterns. The right eye polarized patterns are disposed corresponding to the right eye pixel structures, and the left eye polarized patterns are disposed corresponding to the left eye polarized patterns. An edge of each right eye polarized pattern overlaps with the second region of the corresponding right eye pixel structure. An edge of each left eye polarized pattern overlaps with the second region of the corresponding left eye pixel structure.

Transparent stereo display and operation method thereof

A method for cleaning a cache of a processor includes: generating a specific command according to a request, wherein the specific command includes an operation command, a first field and a second field; obtaining an offset and a starting address according to the first field and the second field; selecting a specific segment from the cache according to the starting address and the offset; and cleaning data stored in the specific segment.

Method for cleaning cache of processor and associated processor

A liquid crystal display panel has a display region and a peripheral region defined thereon. The peripheral region is disposed at an outside of the display region, and the peripheral region includes a bridge circuit region. The liquid crystal display panel includes a first substrate, a first conductive layer, a second substrate, a second conductive layer and a spacer. The first conductive layer is disposed on the first substrate in the bridge circuit region. The second substrate is disposed in parallel to a side of the first substrate, and the second conductive layer is disposed on the second substrate in the peripheral region. The spacer is disposed between the first conductive layer and the second conductive layer in the bridge circuit region, and the spacer electrically isolates the first conductive layer from the second conductive layer.

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Hsinchu, Taiwan

Chao-Wei Huang