Wuhan China Star Optoelectronics Technology Co., Ltd.

Other

Huawei Technologies Co., Limited

Yangtze Memory Technologies Co., Ltd.

Wuhan Neuracom Technology Development Co., Ltd.

Chao Wang

Guanghui Liu

Wenqiang Yu

Xindong Mei

Yantao Lu

Shaojun Hou

Peng Zhang

Caiqin Chen

Qiang Gong

Gui Chen

Yuan Sun

Liwang Liu

Zhifu Li

Chunhui Zhang

Qipei Zhang

Yuan Yan

Li Huang

Cheng Huang

Weihong Yin

He Jiang

Chunqian Zhang

Hailong Pan

Quan Tang

Lewei Zhang

Jiakuai Bian

Youdong Jiang

Yulong Zhang

Zhiyong Suo

Jianfei Gao

Chunshui Wang

Guangyan Cai

Disclosed are a reverse soldering connection structure of a microneedle and a wiring and a preparation process thereof. The reverse soldering metal layer of the microneedle is prepared; the reverse soldering metal layer of the wiring is prepared; the reverse soldering metal layer of the microneedle is aligned with the reverse soldering metal layer of the wiring, and they will be pressed to achieve reverse soldering connection between the microneedle and the wiring.

Reverse soldering connection structure of microneedle and wiring and preparation process therefor

A display panel and a display terminal are provided. The display panel includes a substrate, a first metal layer disposed on the substrate, and a second metal layer disposed above the first metal layer. The first metal layer includes a plurality of data lines extending in a first direction and thin-film transistors each including a source electrode. The source electrode is electrically connected to a corresponding one of the data lines. The second metal layer includes a drain electrode of the thin-film transistor, and the drain electrode is located between adjacent ones of the data lines.

Display panel and display terminal

A method of wafer bonding includes: forming a first hole in a first insulation layer disposed over a first substrate; performing a first deposition-self-etch process to deposit a first conductive material in the first hole to form a first conductive plug; forming a second hole in a second insulation layer disposed over a second substrate; performing a second deposition-self-etch process to deposit a second conductive material in the second hole to form a second conductive plug; and bonding the first conductive plug with the second conductive plug to form a first grain fusion layer between the first conductive plug and the second conductive plug.

Wafer bonding method and bonded wafer

A backlight module and a display device are provided, which include a camera area and a backlight area, wherein the backlight area surrounds the camera area, the camera area includes a transparent illumination area and a non-transparent illumination area, and the non-transparent illumination area surrounds the transparent illumination area; and the light board is disposed in the non-transparent illumination area and the at least one light bead is disposed on a light board. In the display mode, the camera area obtains a uniform light source, so as to realize the camera area of the display device which can be displayed normally in the displaying mode, and achieve a true 100% screen ratio. In a lighting mode of the camera module, the light source of the light bead is turned off to avoid affecting the collecting operation of the camera module.

Backlight module and display device

A display panel is provided. The display panel includes a substrate, and a data line and a transistor electrically connected to the data line and on the substrate, and the transistor includes a patterned active layer and a conductive line. The patterned active layer of the transistor is disposed in a region corresponding to the data line. The patterned active layer includes a source contact region, the conductive line includes a first conductive line that is a source electrically connected to the patterned active layer corresponding to the source contact region, and an orthographic projection of the source on the substrate is located within an orthographic projection of the data line on the substrate.

Display panel with transistor disposed in region corresponding to data line

A display panel and a display device are provided. The display panel includes an active layer, a gate electrode layer, and a metal layer. By forcibly pulling down an electrical potential of a scan signal in a first scan line when a pulse rising edge of the scan signal in the second scanning line arrives, an electrical potential falling time of each scan signal in a display area can be shortened. At the same time, a control line is constructed to at least partially overlaps an electrical potential transmission line in a thickness direction of the display panel, to increase an aperture ratio as much as possible.

Display panel and display device

The present application provides a display panel and a display device. The display panel includes a plurality of data lines and a first demultiplexer. In the first demultiplexer, each first channel wire is connected to at least two data lines. Each first control unit includes a plurality of first switching elements. At least one data line is connected to the first channel wire through M first switching elements connected in parallel, and M≥2. The display panel includes a display area, and the first control unit is arranged in the display area.

A display panel includes a first data line, a second data line, a third data line, a first sub-pixel, a second sub-pixel, a third sub-pixel, and a first transistor. The first sub-pixel is located between the first data line and the second data line, and includes a first pixel electrode. The second sub-pixel is located between the second data line and the third data line, and includes a second pixel electrode. The third sub-pixel is located between the first data line and the second data line, and includes a third pixel electrode. The first transistor is electrically connected to one of the first pixel electrode, the second pixel electrode, and the third pixel electrode. The first transistor includes a first semiconductor. At least a part of the first semiconductor overlaps with the first pixel electrode or the second pixel electrode.

Display panel

The present disclosure provides a display panel. The display panel includes a data line; a transistor electrically connected to the data line, wherein the transistor includes a patterned active layer disposed in an area corresponding to the data line; and a shielding layer disposed between the patterned active layer and the data line.

A display panel and a display device are provided. The display panel includes a plurality of scan lines extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixel units. Each of the pixel units comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel disposed between adjacent two of the scan lines. The first sub-pixel and the second sub-pixel are arranged along the first direction, and the first sub-pixel and the third sub-pixel are arranged along the second direction.

The present invention discloses a display panel and an electronic terminal. The display panel includes a first display region and a second display region. The second display region includes a plurality of display subregions. Each of the plurality of display subregions includes a display portion and a light-transmitting portion. Each of the plurality of display subregions includes a switch control unit, a liquid crystal layer, a transparent electrode group, and a color filter layer. The liquid crystal layer is disposed in the display portion and the light-transmitting portion. The transparent electrode group is configured to control a deflection direction of liquid crystal molecules in the liquid crystal layer, which puts the light-transmitting portion in a light-transmitting state or an opaque state.

Display panel and electronic terminal

The present invention discloses a display device including an optical film including a through hole; a display panel disposed on a surface of one side of the optical film, wherein the display panel includes a transparent area corresponding to the through hole; a camera including a camera lens, wherein the camera is inserted into the through hole and faces the transparent area; and a plurality of LED chips evenly arranged around the camera lens, wherein the LED chips are disposed in the through hole and between the camera and the transparent area.

Display device including LED chips around camera lens

A display panel is provided and includes an array substrate and a display region located on a surface of the array substrate, wherein a portion of the array substrate not occupied by the display region forms a bezel, and a driving chip and a flexible circuit board are bound in the bezel; wherein at least one a protrusion is formed at an end of the bezel away from the display region, the driving chip is located between an edge of the protrusion and an edge of the display region; and a portion of the flexible circuit board is bent to a back of the array substrate via an edge of an indent on at least one lateral side of the protrusion.

A display panel is provided. The display panel comprises a display screen, a first backlight module, a second backlight module, and a fingerprint sensor, wherein the second backlight module has a fingerprint identification mode and a display mode. In the fingerprint identification mode, light reaches the fingerprint sensor through the second backlight module for fingerprint identification, and in the display mode, the first backlight module and the second backlight module provide uniform backlight to the display screen, thus realizing compatibility of functions of under-screen fingerprint identification and display.

A display panel and method of manufacturing the same are provided. The method of manufacturing the display panel includes the steps of providing a substrate, forming a gate on the substrate, forming a gate insulating layer on the gate and the substrate, forming a polysilicon layer on the gate insulating layer, performing a first gray-scale mask process on the polysilicon layer to form a source region, a drain region and an active region located between the source region and the drain region by the polysilicon layer, forming an interlayer dielectric layer on the gate insulating layer and the polysilicon layer, forming a first electrode layer on the interlayer dielectric layer, performing a second gray-scale mask process on the first electrode layer and the interlayer dielectric layer.

Growing community of inventors

Wuhan, China

Chao Wang