Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Chao Sun

Dejan Vucinic

Minghai Qin

Zvonimir Z Bandic

Yan Li

Xinde Hu

Viacheslav Anatolyevich Dubeyko

Pi-Feng Chiu

Robert Eugeniu Mateescu

Qingbo Wang

Seung-Hwan Song

Tung Thanh Hoang

Pietro Bressana

Anand Kulkarni

Pankaj Mehra

Yongke Sun

Vidyabhushan Mohan

Adam Manzanares

Frank R Chu

Arup De

Huynh Tu Dang

Jaco Hofmann

Wen Pan

Muqing Liu

A Data Storage Device (DSD) includes a first memory storing reference files used to derive vector embeddings in a vector database. A query vector embedding is received from a host and one or more vector embeddings similar to the query vector embedding are identified in the vector database. One or more reference files from which the one or more vector embeddings were derived are identified and stored in a second memory for faster access. In another aspect, a query vector embedding is received by a host that identifies one or more vector embeddings that are similar to the query vector embedding and retrieves the one or more vector embeddings from a DSD to provide to an Artificial Intelligence (AI) model. One or more reference files are identified from which the one or more vector embeddings were derived and are prefetched from the DSD for storage in a host memory.

Reference file management for artificial intelligence models

Devices and methods to implement semantic searching on SSD through a computational SSD system that distributes computing to each NAND flash die of the SSD while the SSD controller handles the results aggregation with new on-die computation logic circuits to provide on device file semantic search are disclosed herein. The computational SSD system can read file feature vectors from multiple dies to the SSD controller, and if needed, these feature vectors may be buffered in DRAM and controller handles distance computing. Local, on-die AI/ML processing units may perform, for example, computation and comparison operations and pass the processing scores and results to the SSD controller. The SSD controller aggregates results from all dies and returns the result to the host. The feature vector store size, circuitry and number of on-die AI/ML processing units may be configured as needed to adapt to different tasks, system constraints, and/or feature vector sizes.

Error correction methods for computational SSD supporting rapid file semantic search

A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.

Memory prefetch based on machine learning

Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply analog weights to input data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the analog weights. The device also comprises a device controller configured to program the analog weights to the CIM module, cause the CIM module to process the input data, and reprogram one or more analog weights that are degraded. The digital weight references in the digital weight storage unit are populated with values from a host processing device. Degraded analog weights in the CIM module are reprogrammed based on the corresponding digital weight references from the digital weight storage unit without reference to the host processing device.

Systems and methods of compensating degradation in analog compute-in-memory (ACIM) modules

A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged in a plurality of logical planes and the controller is configured to write log data and user data to separate planes within the memory device, such that the log data and user data are isolated from each other on separate planes. The controller is configured to read log data from one plane and user data on another plane simultaneously, where the log data and the user data are isolated from each other on separate planes.

Storing log and user data in SSD with independent plane operations

A programmable network switch includes at least one pipeline including a packet parser configured to parse packets, and a plurality of ports for communication with network devices including a plurality of Data Storage Devices (DSDs). A packet comprising a write command is received to store data in a DSD of the plurality of DSDs, and an identifier generated for the data is compared to a plurality of identifiers generated for data stored in the plurality of DSDs. It is determined whether to send the write command to store the data to the DSD based on whether the generated identifier matches an identifier of the plurality of identifiers. In one aspect, the data to be stored for the write command is extracted from the packet using a pipeline of the programmable network switch, and at least a portion of the extracted data is used to generate the identifier for the data.

In-line data identification on network

Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply a plurality of analog weights to data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the plurality of analog weights. The device also comprises a device controller configured to program the plurality of analog weights to the CIM module based on the digital weight references and determine degradation of one or more analog weights. The digital weight references in the digital weight storage unit are populated with values from a host device. Degraded analog weights in the CIM module are replaced with corresponding digital weight references from the digital weight storage unit without reference to the host device.

Systems and methods of determining degradation in analog compute-in-memory (ACIM) modules

An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a current value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

3-dimensional NAND flash layer variation aware SSD raid

In some implementations, the present disclosure relates to a method. The method includes obtaining a set of weights for a neural network comprising a plurality of nodes and a plurality of connections between the plurality of nodes. The method also includes identifying a first subset of weights and a second subset of weights based on the set of weights. The first subset of weights comprises weights that used by the neural network. The second subset of weights comprises weights that are prunable. The method further includes storing the first subset of weights in a first portion of a memory. A first error correction code is used for the first portion of the memory. The method further includes storing the second subset of weights in a second portion of the memory. A second error correction code is used for the second portion of the memory. The second error correction code is weaker than the first error correction code.

Optimized neural network data organization

A data storage device includes a memory device that includes a plurality of zones of a zoned namespace and a controller coupled to the memory device. During operation, the controller maintains a window-based read and write monitor data structure to determine the read density and write density of each of the zones. The read density and write density are utilized to determine a cost for allocating wear leveling data for each zone. Based on the cost and the available storage capacity of the storage class memory, data, in a data management operation, is moved to either the storage class memory or the zone with the low cost. The host device is informed of the storage class memory usage for future data management operations.

Wear leveling methods for zoned namespace solid state drive

A programmable network switch includes at least one pipeline including a packet parser configured to parse packets received by the programmable network switch. The programmable network switch further includes a plurality of ports for communication with a plurality of Data Storage Devices (DSDs). Packets comprising commands are received by the programmable network switch to perform at least one of retrieving data from and storing data in the plurality of DSDs. The commands are sent by the programmable network switch to the plurality of DSDs via the plurality of ports, and the use of each port for sending the commands is monitored. According to one aspect, it is determined which port to use to send a command based on the monitored use of at least one port of the plurality of ports.

In-line data operations for storage systems

A memory array controller includes memory media scanning logic to sample a bit error rate of memory blocks of a first memory device. A data management logic may then move data from the first memory device to a second memory device if the bit error rate matches a threshold level. The threshold level is derived from a configurable data retention time parameter for the first memory device. The configurable data retention time parameter may be received from a user or determined utilizing various known machine learning techniques.

Retention-aware data tiering algorithm for hybrid storage arrays

A device includes a Storage Class Memory (SCM) and a secondary memory with at least one of a greater read or write latency than the SCM. At least a portion of the SCM is provided as an address space of a processor. An SCM smallest writable unit for writing data in the SCM is smaller than a secondary memory smallest writable unit for writing data in the secondary memory. An operation instruction is received from the processor to perform an operation on data stored in the secondary memory. The data is loaded from the secondary memory into the SCM for performance of the operation.

Data access in data storage device including storage class memory

An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.

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San Jose, CA, United States of America

Chao Sun