Vanguard International Semiconductor Corporation

Industrial Technology Research Institute

Chao-Ming Koh

Jia-Ching Doong

Rong-Wu Chien

Bin Liu

Yeh-Sen Lin

Hao-Cheng Hung

Ting Chou

Gia-Hua Hsieh

Hsien-Tzu Chang

Yung-Song Lou

Ching-Cherng Rou

Chuen-Nan Chen

Shin-Chi Lee

Fu-Liang Yang

Wen-Shiang Liao

Erik S Jeng

Yu-Hua Lee

Ching-Ying Lee

Daniel Hao-Tien Lee

Yu-Chun Ho

Wen-Jya Liang

Tung Chia Ching

Hsiao-Chiu Tuan

Chan-Jen Kno

George Wen Liang

Chun-Ju Huang

A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common polysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common polysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common polysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

Non-volatile memory cell and method of forming the same

A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switching device and the first and second plane capacitors share a common ploysilicon floating gate configured to retain charge as a result of programming the memory cell. The memory cell is configured to be erased by tunneling between the first doped region and the common ploysilicon floating gate without causing junction breakdown within the memory cell. The first and second doped regions are formed in the substrate before forming the common ploysilicon floating gate such that the capacitance of the first and second plane capacitors are constant when the memory cell operates within an operating voltage range.

A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first Mag., followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof

A method for fabricating Fiber Bragg Grating elements and planar light circuits made thereof. A mask having a predetermined pattern and a wafer are provided, wherein a light-guiding channel filled with light-guiding substance is formed on the wafer. A photoresist layer is then formed to cover the wafer. Magnification of a photolithography apparatus is adjusted to a first magnification, followed by transferring the pattern on the mask to the photoresist layer to form a first pattern. Light-guiding substance not covered by the photoresist layer is then removed so that the first pattern is transferred to the light-guiding channel. The light-guiding channel then forms a Fiber Bragg Grating element.

Method for fabricating fiber bragg grating elements and planar light circuits made thereof

A nonvolatile memory device with a high coupling ratio is disclosed. The nonvolatile memory device includes a semiconductor substrate having shallow trench isolation (STI) formed therein and active regions defined. On the active regions, a floating gate is provided with a gate dielectric layer interposed. On the floating gate, a control gate is provided with a second dielectric layer interposed. The width of the floating gate is narrower than the active regions when viewed in transverse cross-section. A lighted doped region is optionally provided in the substrate at positions which are not covered by the floating gate. A manufacturing method for forming such memory device is also disclosed.

Nonvolatile memory device and manufacturing method thereof

A method for manufacturing a photomask of cylindrical capacitor arrays surrounded by a corrugated protection trench is provided. First, a capacitor array layout is generated, next, the capacitor array patterns are copied to protection trench area with exact the same shape and pitch, finally, the protection trench is finished by filling connecting patterns between gaps of the capacitor arrays. A corrugated close loop protection trench pattern can hence be developed upon photoresist through the exposing and is developing of a photo stepper.

Photomask method for making the same capacitor cell area near outmost cell arrays

A method of making a nonvolatile memory device having a high capacitive coupling ratio with a self-aligned floating gate is disclosed. A tunnel dielectric layer, a first conductive layer, and a sacrificial layer are sequentially formed over a semiconductor substrate. Isolation trenches are etched in the substrate through the layers and filled with isolation oxides that protrude over the substrate. Subsequently, the sacrificial layer is removed to leave a cavity between the isolation oxides. A second conductive layer is conformally deposited over substrate, and then planarized or etched back to the isolation oxides. Next, the isolation oxides are etched back to expose additional surface of the second conductive layer. Finally, an inter-gate dielectric layer and a control gate layer are sequentially formed over the substrate.

Method of making nonvolatile memory having high capacitive coupling ratio

A MOSFET device fabricated by a method that reduces, the risk of gate to source and drain bridging, has been developed. The process features fabricating a polysilicon structure, which is wider at the top than at the bottom, with a source and drain region, self-aligned to the narrower, underlying polysilicon layer. Subsequent metallization results in metal coverage, only on the surfaces of the wider polysilicon layer. An anneal cycle then converts only the wider polysilicon feature to a metal silicide, resulting in a polycide gate structure, comprised of a wider, overhanging metal silicide layer, on a narrower, underlying polysiliocn layer.

Method to ensure isolation between source-drain and gate electrode using self aligned silicidation

A process for forming a cylindrical shaped, storage node structure, for a DRAM capacitor, has been developed. The process features forming a capacitor opening, in an insulator layer, exposing the fop surface of a storage node plug structure, located at the periphery of the capacitor opening. The deposition of a conductive layer, followed by a blanket, anisotropic RIE procedure, results in the creation of a cylindrical shaped, storage node structure, on the sides of the capacitor opening, with contact to the underlying storage node plug structure, accomplished via a segment of the cylindrical shaped, storage node structure, overlying a portion of the top surface of the underlying storage node plug structure. The cylindrical shaped, storage node structure described on this invention, is formed without the use of the costly CMP procedure, and without the use of the costly and complex, photoresist plug, used to protect the bottom portion of a storage node structure, employed for the fabrication of counterpart, crown shaped storage node structures.

Method of forming a ring shaped storage node structure for a DRAM

A process for forming a DRAM capacitor structure, comprised with a HSG silicon/polysilicon crown shaped storage node structure, has been developed. The process features the use of a series of wet clean procedures, used to prepare the surface of the HSG silicon/polysilicon, crown shaped storage node structure, for the formation of an overlying capacitor dielectric layer. A first wet clean procedure is employed after the formation of the crown shaped storage node structure via a CMP procedure, featuring an ammonium hydroxide--hydrogen peroxide solution, used to remove CMP, as well as HSG silicon particles from the surface of a photoresist plug used for definition of the crown shaped storage node structure. Another wet clean procedure, first performed in a DHF solution, then followed by a sulfuric acid--hydrogen peroxide treatment, is used to prepare the HSG silicon/polysilicon, crown shaped storage node structure, for formation of the overlying capacitor dielectric layer.

Post chemical mechanical polishing, clean procedure, used for

A method for forming a storage capacitor within an integrated circuit cell. There is first formed upon a semiconductor substrate an integrated circuit cell. The integrated circuit cell has formed therein a Field Effect Transistor (FET) which has an exposed source/drain electrode. The semiconductor substrate also has formed therein at least one other integrated circuit device which has at least one exposed contact electrode. There is then formed upon the semiconductor substrate a blanket conductor layer. The blanket conductor layer is then patterned to form a first portion of the blanket conductor layer and a second portion of the blanket conductor layer separate from each other. The first portion of the blanket conductor layer forms a patterned conductor layer contacting the exposed contact electrode of the other integrated circuit device. The second portion of the blanket conductor layer simultaneously forms a storage capacitor node contacting the exposed source/drain electrode of the Field Effect Transistor (FET). A storage capacitor within the integrated circuit cell may then be completed by forming a storage capacitor dielectric layer upon the storage capacitor node and subsequently forming a storage capacitor plate layer upon the storage capacitor dielectric layer.

Method for forming a storage capacitor within an integrated circuit

A novel raised polycide fusible link structure is described. This structure enables a highly reliable laser-cutting process to be used in which the fuse can be easily and totally severed over a wide range of laser energy levels. The primary feature of the structure is that the fusible link is located on a pedestal that raises it above the surface of the main body of the integrated circuit, thereby providing a measure of thermal isolation for the fuse when it is irradiated by the laser. An efficient process for manufacturing the structure is also described.

Raised fuse structure for laser repair

A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor. The fin structure is then used as a mask to anisotropically etch the bottom polysilicon layer, and thereby complete and electrically isolate the bottom fin-shaped electrodes. The capacitor is completed by forming the inter-electrode dielectric and depositing a top electrode layer.

Method of manufacturing a stacked capacitor having a fin-shaped storage

The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using the side wall polymers and the etching byproductions as a mask to form the crown shape capacitors with pillars. Moreover, this present invention can form the crown shape structure and pillars in the same step, the crown shape structure and the pillars increase the surface area of the capacitor. Therefore the present invention will increase the performance of the capacitor.

Method of manufacturing a crown shape capacitor in semiconductor memory

A method of forming a capacitor on a semiconductor substrate includes forming a first oxide layer on the semiconductor substrate. A contact hole is then formed in the first oxide layer. A first conductive layer is formed on the first oxide layer and in the contact hole. Then the first conductive layer is etched to form a node structure. A non-conformal oxide is formed on the node structure so that the non-conformal oxide has an overhang portion and a lower portion on the sidewall of the node structure. The non-conformal oxide is isotropically etched to remove the lower portion of the non-conformal oxide and to expose the lower sidewall of the node structure. A second conductive layer is conformally deposited on the non-conformal oxide layer and the lower sidewall of the node structure. The second conductive layer is anisotropically etched, using the overhang portion of the non-conformal oxide as a mask. Then the non-conformal oxide is removed by using a highly selective etching process. The resulting conductive structure serves as a bottom storage node of the capacitor. A dielectric film is formed on the first conductive layer and the second conductive layer. A third conductive layer is formed over the dielectric film to form the top storage node of the capacitor.

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Hsinchu, Taiwan

Chao-Ming Koh