Subtron Technology Co., Ltd.

Synopsys, Inc.

Chao-Min Wang

Chin-Sheng Wang

Ching-Sheng Chen

Hsin-Po Wang

Chun-Kai Lin

Hung-Shih Wang

Song Yuan

Ru-Lin Yang

Cheng-Lin Lee

Yuan-Wen Wang

Net-based checking of a circuit design includes obtaining a circuit design comprising a plurality of polygons. Further, a shape of a first polygon of the plurality of polygons, and a shape of a second polygon of the plurality of polygons is determined. The shape of the first polygon differs from a shape of the second polygon. Violations within the circuit design are detected based on a comparison of the first polygon with the second polygon.

Constraint file-based novel framework for net-based checking technique

A computer implemented method for routing a multitude of conductors through a first routing area on a planar surface is presented. The method includes receiving data representing the first routing area bounded by two opposite longitudinal sides each having a different number of a multitude of first vertices. The first routing area includes one or more blockages. The method further includes determining one or more locations on at least one of the two opposite longitudinal sides for adding one or more second vertices, and decomposing the first routing area into a multitude of second routing areas each not including any of the one or more blockages. The method further includes performing a gateway model routing (GMR) of the multitude of conductors in each of the multitude of second routing areas using the multitude of first vertices and the added one or more second vertices.

Creating gateway model routing sub-templates

A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer, a release layer and a second patterned solder-resist layer. The dielectric layer includes a first surface having a plurality of recesses and a second surface. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.

Substrate structure

A manufacturing method of a package carrier is provided. A carrier having a connecting surface is provided. A releasable solder resist layer is formed on the connecting surface of the carrier and completely covers the connecting surface. A substrate having an upper surface and a lower surface opposite to each other is provided. A first patterned solder resist layer is formed on the lower surfaces of the substrate and exposes a portion of the lower surface. The carrier and the substrate are laminated, the releasable solder resist layer directly contacts the first patterned solder resist layer, and the carrier is temporarily bonded to the first patterned solder resist layer through the releasable solder resist layer.

Package carrier and manufacturing method thereof

A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer and a second patterned solder-resist layer. The dielectric layer includes a first surface and a second surface, and the first surface has a plurality of recesses. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.

Substrate structure and manufacturing method thereof

A substrate structure is provided. The substrate structure includes a substrate and a carrier. The substrate includes a first through hole, a first surface and a second surface opposite to the first surface. The first through hole penetrates the substrate for connecting the first surface and the second surface. The carrier includes a second through hole, a release layer, an insulating paste layer and a metal layer. The insulating paste layer is disposed between the release layer and the metal layer. The carrier is attached to the second surface with the release layer thereof. The second through hole corresponds to the first through hole and penetrates the carrier for exposing the first through hole.

A package carrier including a removable supporting plate and a circuit board is provided. The removable supporting plate includes a dielectric layer, a copper foil layer and a releasing layer. The dielectric layer is disposed between the copper foil layer and the releasing layer. The circuit board is disposed on the removable supporting plate and directly contacts the releasing layer. A thickness of the circuit board is between 30 &#x3bc;m and 100 &#x3bc;m.

Package carrier

A manufacturing method of a substrate structure includes the following steps. A substrate including a supporting layer, two release layers and two base metal layers is provided. The release layers are disposed on two opposite surfaces of the supporting layer respectively. Each base metal layer covers each of the release layers. A first patterned solder-resist layer is formed on each of the base metal layers. A stacking layer is laminated on each of the base metal layers to cover each of the first patterned solder-resist layers. Each stacking layer includes a dielectric layer and a metal foil. Each dielectric layer is disposed between the corresponding base metal layer and the corresponding metal foil. Each base metal layer is separated from the supporting layer. Each base metal layer is patterned to form a patterned metal layer on each stacking layer. Each patterned metal layer exposes the corresponding first patterned solder-resist layer.

A core substrate includes a dielectric layer, at least one releasing layer, at least one first copper foil layer and at least one nickel layer. The releasing layer is disposed on the dielectric layer and directly covers the dielectric layer. The first copper foil layer is disposed on the releasing layer and directly covers the releasing layer. The nickel layer is disposed on the first copper foil layer and directly covers the first copper foil layer.

Core substrate and method for fabricating circuit board

A circuit board includes a circuit layer, a first solder resist layer, a second solder resist layer and at least one conductive bump. The first solder resist layer is disposed on a lower surface of the circuit layer and has at least one first opening exposing a portion of the lower surface of the circuit layer. The second solder resist layer is disposed on an upper surface of the circuit layer and has at least one second opening exposing a portion of the upper surface of the circuit layer. The conductive bump is disposed inside the second opening of the second solder resist layer and directly connects to the upper surface of the circuit layer exposed by the second opening. A top surface of the conductive bump is higher than a second surface of the second solder resist layer.

Circuit board and manufacturing method thereof

A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.

Growing community of inventors

Hsinchu County, Taiwan

Chao-Min Wang