Realtek Semiconductor Inc.

Chao-Min Lai

Chien-Liang Chen

Hung-Wei Wang

Han-Chieh Hsieh

Ming-Tsung Tsai

Ping-Chia Wang

Tang-Hung Chang

Chun-Yi Kuo

Yu-Jen Lin

Chia-Chi Yeh

Shou-Te Yen

Shih-An Yang

Cheng-Yu Lee

Chih-Feng Lin

Cheng-Chen Huang

Chia-Hao Wu

Guo-Yuan Luo

Yan-Jyun Chen

Chieh-Lung Hsieh

Nan-chin Chuang

Huang-lin Kuo

Tang-hung Chang

Han-chieh Hsieh

A multimedia device comprises a power input interface, a computing circuit and a load circuit. The power input interface is configured to receive an operating voltage. The computing circuit is configured to receive the operating voltage from the power input interface, and configured to output a pulse-width modulation (PWM) signal. The load circuit is configured to receive a test current from the power input interface, receive the PWM signal, and determine a magnitude of the test current according to a duty ratio of the PWM signal. The computing circuit is configured to monitor the variation of the operating voltage while adjusting the duty ratio of the PWM signal step by step. The computing circuit is configured to determine an upper bound of a power consumption of the computing circuit according to the relationship between the operating voltage and the duty ratio of the PWM signal.

Multimedia device and operating method for system-on-chip

A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.

SoC with UART interface

An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.

Electronic system and determination method capable of determining reason of cold boot event

A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Media streaming device and media streaming method

A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

Package substrate and chip package structure using the same

A power supply circuit includes a first regulator and a second regulator. The first regulator is configured to generate a first output signal according to an input signal. A voltage value of the first output signal decreases according to the input signal and a first voltage threshold value at a power-off stage. The second regulator is configured to be enabled according to the first output signal to generate a second output signal according to the input signal. A voltage value of the second output signal decreases according to the input signal and a second voltage threshold value at the power-off stage. The second voltage threshold value is greater than the first voltage threshold value.

Power supply circuit

The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Processor with adjustable operating frequency

The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

Adaptive voltage scaling scanning method and associated electronic device

An audio receiver includes a first signal port, a second signal port, a power supply port, a power ground port, and an amplifier circuit. The first signal port is coupled to an audio signal line of a transmission interface. The second signal port is coupled to an audio ground line of the transmission interface. The power supply port is coupled to a power supply line of the transmission interface to generate a power supply level to the power supply line. The power ground port is connected to the ground level and to a power ground line of the transmission interface. When the audio receiver is outputting a power supply current to the audio source device through the power supply port via the power supply line, a connection state between the second signal port and the power ground port is at a high impedance state.

Method and audio receiver capable of effectively reducing or avoiding current noise

A circuitry applied to an electronic device having a Universal Serial Bus (USB) type-C connector is provided. The circuitry includes a transceiver circuit, a physical layer circuit and a processing circuit. In operations of the circuitry, the transceiver circuit is coupled to the USB type-C connector. The physical layer circuit is configured to directly utilize a plurality of first signals from the USB type-C connector as at least one portion of Ethernet signals, and process the first signals to generate a plurality of processed first signals. The processing circuit is configured to process the processed first signals to generate an output signal.

Circuitry applied to electronic device having USB type-c connector and associated electronic device

A performance management method and an electronic device are provided. The method is applied to the electronic device with a system processor and includes: sensing a temperature of the electronic device and determining whether the temperature is greater than a first temperature setting value; when the temperature is not greater than the first temperature setting value, initiating a frequency increasing procedure; when the temperature is greater than the first temperature setting value, determining whether the temperature is greater than a second temperature setting value, where the second temperature setting value is greater than the first temperature setting value; when the temperature is greater than the first temperature setting value and is not greater than the second temperature setting value, initiating a first frequency reducing procedure; and when the temperature is greater than the second temperature setting value, initiating a second frequency reducing procedure or turning off the system processor.

Power performance management method and electronic device

A control device and a circuit board are provided. The control device can cooperate with the circuit board, and includes a ball grid array. The ball grid array includes a plurality of power balls and a plurality of ground balls, which are jointly arranged in a ball region. The power balls and the ground balls are respectively divided into a plurality of power ball groups and a plurality of ground ball groups. One of the ground ball groups includes two ground balls and is adjacent to a power ball group. A ball pitch between the two ground balls is greater than that between one of the power balls and one of the ground balls adjacent to each other. The circuit board includes a contact pad array corresponding to the ball grid array of the control device so that the control device can be disposed on the circuit board.

Control device and circuit board

A media streaming device is provided that includes a media streaming module, a super capacitor and a protection module. The media streaming module provides the media stream. The super capacitor has a first terminal coupled to a power-supplying path and a second terminal coupled to a ground terminal. The protection module includes a current limiter and a disabling unit. The current limiter receives a power signal and performs current-limiting to generate a fixed-current power to charge the super capacitor and supply power to the media streaming module through the power-supplying path. The current limiter further detects a voltage of the first terminal of the super capacitor. The disabling unit disables the media streaming module when the voltage of the first terminal of the super capacitor is not higher than a voltage threshold value, and enables the media streaming module when the voltage is higher than the voltage threshold value.

Media streaming device and protection method of the same

A signal processing circuit includes: a printed circuit board (PCB) including a first surface layer, a second surface layer, a first reference layer, and a second reference layer, wherein the first and second surface layers are positioned on opposing side of the PCB while the first reference layer and the second reference layer are positioned between the first and second surface layers; a memory chip positioned on the first surface layer; a controller chip positioned on the second surface layer; a first set of signal lines arranged on the first surface layer and coupled with the memory chip, wherein all signal lines in the first set of signal lines does not cross each other; and a second set of signal lines arranged on the second surface layer and coupled with the controller chip, wherein all signal lines in the second set of signal lines does not cross each other.

Signal processing circuit capable of avoiding cooperating memory chip from performance degradation

An electronic apparatus and a circuit board thereof are provided. The electronic apparatus includes a control device that can operate with the circuit board, and includes a ball pad array. The ball pad array includes a plurality of power ball pads and a plurality of ground ball pads, which are arranged in the same pad arrangement region. At least a portion of the power ball pads and at least a portion of the ground ball pads are arranged in an alternate manner. The circuit board includes a solder pad array corresponding to the ball pad array of the control device so as to be disposed with the control device.

Growing community of inventors

Hsinchu, Taiwan

Chao-Min Lai