Macronix International Co., Ltd.

Chao-Lung Lo

Tzong-Hsien Wu

ChungTe Hsuan

Kuang-Chao Chen

Ta-Hung Yang

Tahone Yang

Tien-Chu Yang

Sunwook Jung

Yi-Yien Tsai

Chien Hung Chen

A target pattern is provided including a first pattern in a first region. A sensor pattern is inserted in the target pattern in the first region. A flare intensity of the sensor pattern in the first region is determined. A pattern bias is determined based on the flare intensity.

Flare effect induced error correction

A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout.

System and method for optical proximity correction of a modified integrated circuit layout

A method and system to form openings comprises an exposure apparatus and a mask to selectively expose a semiconductor substrate to a radiation source to transfer assist feature patterns and primary feature patterns to a photosensitive layer of the substrate. A heating apparatus eliminates the assist features by heating the substrate and shrinking the primary features. The patterns on the photosensitive layer are transferred to a layer under the photosensitive layer by an etching process.

Method and system for manufacturing openings on semiconductor devices

The invention is directed to a method for designing an assistant pattern of a mask pattern on a mask. The mask pattern has an assistant pattern arrangement region around a main pattern. The method comprising defining a reverse pattern of the main pattern. The reverse pattern is shrunken to be a first shrunken pattern with a first shrinking proportion and a first margin placed within the assistant pattern arrangement region. The reverse pattern is shrunken to be a second shrunken pattern with a second shrinking proportion and a second margin placed within the assistant pattern arrangement region. The first shrunken pattern and the second shrunken pattern are merged to define an assistant pattern of the mask pattern, wherein the assistant pattern entirely surrounds the main pattern.

System for designing mask pattern

A method of deriving etching correction values for the patterns of a photomask and a method of fabricating a photomask are described. The former method includes the following steps. The layout data of the photomask are provided, and local etching correction values of respective patterns are determined from the pattern configurations at respective areas of the photomask. A global etching correction value is determined from a wafer coverage ratio calculated mainly from the layout data. The local etching correction values of the respective patterns are added with the global etching correction value to obtain total etching correction values of the respective patterns. In the method of fabricating a photomask, the layout data are subjected to an etching correction based on the total etching correction values of the respective patterns and then to an optical proximity correction, and the photomask patterns are formed based on the resulting layout data.

Method of deriving etching correction values for patterns of photomask and method of fabricating photomask

The invention is directed to a pattern on a mask. The pattern comprises a main dense pattern, a first anti-aberration pattern and a second anti-aberration pattern. The main dense pattern comprises a first outmost sub-pattern and a second outmost sub-pattern, wherein the first outmost sub-pattern and the second pattern are not adjacent to each other. The first anti-aberration pattern is located adjacent to the first outmost sub-pattern with a first distance. The second anti-aberration pattern is located adjacent to the second outmost sub-pattern with a second distance, wherein the first distance and the second distance are different from each other.

Anti-aberration pattern and method for manufacturing the same

The invention is directed to a method for controlling a critical dimension of a patterned photoresist layer. The method comprises steps of measuring a critical dimension of a raised pattern in a patterned photoresist layer after a photolithography process is performed on the photoresist layer. A determining process is performed to determine whether the critical dimension is within a critical dimension control limit range, wherein the critical dimension control limit range has a upper control limit and a lower control limit. An adjusting process is performed when the critical dimension is not within the critical dimension control limit range. When the critical dimension is smaller than the lower control limit, a photoresist reflow process is performed. When the critical dimension is larger than the upper control limit a photoresist trimming process is performed.

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Hsinchu, Taiwan

Chao-Lung Lo