Sunplus Technology Co., Ltd.

Wisepal Technologies, Inc.

Chao-Kuei Chuang

Jung Che Chang

A glitch suppressing apparatus is provided. The glitch suppressing apparatus comprises four N-type transistors, four P-type transistors, a first delay circuit, a second delay circuit, a first logic circuit, a second logic circuit and two inverters. The glitch suppressing apparatus uses the specific connection relations and functions of the above components to filter positive glitches and negative glitches in the same circuit, so that the glitch suppressing apparatus can be implemented on a smaller chip area.

Glitch suppressing apparatus

A charge integration algorithmic analog-to-digital converter utilizes one operational amplifier to perform an algorithm analog-to-digital conversation. In a first operating cycle, the ratio of a third capacitor to a fourth capacitor is used as a gain to determine an output voltage and an output bit. The output voltage is held in a first and second capacitors. In the second operating cycle, the ratio of the first capacitor to the second capacitor is used to determine an output voltage and an output bit. The output voltage is held in the third and fourth capacitors. The first and second operating cycles are repeated for generating converted digital data.

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Hsinchu, Taiwan

Chao-Kuei Chuang