Novatek Microelectronics Corp.

Chao-Kai Tu

Tse-Hung Wu

Chia-Wei Su

Sheng Hao Tseng

Tien-Chien Lee

Rong-Sing Chu

The disclosure provides a receiver and an automatic offset cancellation (AOC) method thereof. The receiver includes a receiving channel circuit and an AOC circuit. The receiving channel circuit generates an equalized differential signal including an equalized first-end signal and an equalized second-end signal according to an input differential signal. The AOC circuit detects a peak of the equalized first-end signal to generate a first peak detection result. The AOC circuit detects a peak of the equalized second-end signal to generate a second peak detection result. The AOC circuit compares the first peak detection result with the second peak detection result to generate a comparison result. The AOC circuit compensates a mismatch of an input differential pair in the receiving channel circuit according to the comparison result.

Receiver and automatic offset cancellation method thereof

A data control circuit includes an output stage circuit, a switch circuit, and an impedance module. The output stage circuit outputs a data signal. An input terminal of the switch circuit is coupled to an output terminal of the output stage circuit, and an output terminal of the switch circuit is coupled to a post-stage circuit. According to a control of a control signal, the switch circuit determines whether to transmit the data signal of the output stage circuit to the post-stage circuit. The impedance module is configured in the output stage circuit, configured between the output stage circuit and the switch circuit, or configured in the switch circuit. Here, the impedance module reduces noise flowing from the switch circuit to the output stage circuit.

Data control circuit

A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD.

Clock and data recovery apparatus

An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.

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Hsinchu, Taiwan

Chao-Kai Tu