Chang Gung University

Chao-Kai Chang

Chia-Chi Chu

Wu-Shiung Feng

Herng-Jer Lee

Ming-Hong Lai

A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization

A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders

An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

Interconnect model-order reduction method

A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

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Tao-Yuan, Taiwan

Chao-Kai Chang