Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Jie Tsai

Su-Yu Yeh

Chih-Hao Wang

Carlos H Diaz

Cheng-Yi Huang

Mu-Chi Chiang

Meng-Chang Liu

Hsing-Jui Lee

Chin-Nan Wu

Lu-Chang Chen

Su-Yu Lu

Yu-Sen Chu

Jeng Yang Pan

Chi-Bing Chen

A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (HPO), nitric acid (HNO), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.

Method of high selectivity wet etching of salicides

A method for reducing a dinitrogen (N ) ion concentration in an ion implanter including providing an ion implanter having an ion source chamber for producing source ions said ion source chamber surrounded by a plurality of source magnets having a current supply for altering a position of said source ions; providing a gaseous source of material to the ion source chamber for ionization thereby creating a supply of source ions for implantation; creating a supply of source ions to include dinitrogen (N ) ions and nitrogen (N) ions supplied for implantation; and, increasing a current supply to at least one of the plurality of source magnets such that a ratio of dinitrogen (N ) ions to nitrogen (N) ions supplied for implantation is reduced.

Method reducing the effects of N2 gas contamination in an ion implanter

A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, a low temperature anneal procedure is used to activate indium ions in the initial indium pocket region, and to create a final indium pocket region, featuring a final indium profile. The final indium profile remains unchanged after experiencing subsequent high temperature procedures, such as a post-heavily doped, source/drain anneal. The narrow channel length NMOS devices, fabricated using the low temperature anneal procedure described in this invention, resulted in a reduced Vt roll-off phenomena, when compared to counterpart, narrow channel length NMOS, formed without the benefit of the low temperature anneal procedure.

Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects

Growing community of inventors

Hsin-Chu, Taiwan

Chao-Jie Tsai