Gsi Technology, Inc.

Magic Technologies, Inc.

Other

Chao-Hung Chang

Bob Haig

Lee-Lean Shu

Eli Ehrman

Mu-Hsiang Huang

Patrick Chuang

Avidan Akerib

Lejan Pu

Perng-Fei Yuh

Dan Ilan

Toshio Sunaga

Minh Quang Tran

PoKang Wang

A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

Write data processing methods associated with computational memory cells

A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

Read data processing circuits and methods associated with computational memory cells

A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.

Processing array device that performs one cycle full adder operation and bit line read/write logic features

A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Results processing circuits and methods associated with computational memory cells

A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

Computational memory cell and processing array device using memory cells

A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of 'n' bit lines.

Write data processing circuits and methods associated with computational memory cells

An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

Ultra low VDD memory cell with ratioless write port

A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.

Computational memory cell and processing array device with ratioless write port

A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.

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Sunnyvale, CA, United States of America

Chao-Hung Chang